Application programming interface to deselect storage

ABSTRACT

Apparatuses, systems, and techniques to perform one or more APIs. In at least one embodiment, a processor is to perform an API to deselect storage selected to be used to transfer information between a plurality of fifth generation new radio (5G-NR) computing resources.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation-by-pass application of InternationalPatent Application No. PCT/CN2022/081192, filed Mar. 16, 2022, entitled“APPLICATION PROGRAMMING INTERFACE TO SELECT STORAGE,” the disclosure ofwhich is herein incorporated by reference in its entirety. Thisapplication also incorporates by reference for all purposes the fulldisclosure of co-pending U.S. patent application Ser. No. ______, filedconcurrently herewith, entitled “APPLICATION PROGRAMMING INTERFACE TOSELECT STORAGE” (Attorney Docket No. 0112912-449U50), co-pending U.S.patent application Ser. No. ______, filed concurrently herewith,entitled “APPLICATION PROGRAMMING INTERFACE TO PREVENT DESELECTION OFSTORAGE” (Attorney Docket No. 0112912-449US1), U.S. patent applicationSer. No. ______, filed concurrently herewith, entitled “APPLICATIONPROGRAMMING INTERFACE TO STORE DATA” (Attorney Docket No.0112912-449US2), and co-pending U.S. patent application Ser. No. ______,filed concurrently herewith, entitled “APPLICATION PROGRAMMING INTERFACETO OBTAIN DATA” (Attorney Docket No. 0112912-449US4).

FIELD

At least one embodiment pertains to processing resources for fifthgeneration new radio (“5G-NR”) operations. For example, A processorcomprising one or more circuits to perform an application programminginterface (API) to select storage to be used to transfer informationbetween a plurality of fifth generation new radio (5G-NR) computingresources.

BACKGROUND

Creating interoperability between disaggregated computing resources usedin 5G-NR architecture can use significant time, computing, or humanresources. An amount of time, computing, or human resources used tocreate interoperability between disaggregated computing resources usedin 5G-NR architecture can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram for a network protocol stack, inaccordance with at least one embodiment;

FIG. 2 illustrates a transport abstraction framework, according to atleast one embodiment;

FIG. 3 illustrates a schematic flow diagram for transmission of datausing transport abstraction and a non-zero copy approach, according toat least one embodiment;

FIG. 4 illustrates a schematic flow diagram for transmission of datausing transport abstraction and a zero copy approach, according to atleast one embodiment;

FIG. 5 illustrates a schematic flow diagram for transmission of datausing transport abstraction and a zero copy approach, according to atleast one embodiment;

FIG. 6 illustrates a schematic flow diagram for receiving data usingtransport abstraction and a non-zero copy approach, according to atleast one embodiment;

FIG. 7 illustrates a schematic flow diagram for receiving data usingtransport abstraction and a zero copy approach, according to at leastone embodiment;

FIG. 8 illustrates a schematic flow diagram for receiving data usingtransport abstraction and a non-zero copy approach, according to atleast one embodiment;

FIG. 9 illustrates a schematic flow diagram for receiving data usingtransport abstraction and a zero copy approach, according to at leastone embodiment;

FIG. 10 illustrates a schematic block diagram for mapping transportabstraction APIs to a transport configuration based on PeripheralComponent Interconnect Express (PCIe), according to at least oneembodiment;

FIG. 11 illustrates a schematic block diagram for mapping transportabstraction APIs to a transport configuration based on shared memory,according to at least one embodiment;

FIG. 12 illustrates a schematic block diagram for mapping transportabstraction APIs to a transport configuration based on User DatagramProtocol (UDP), according to at least one embodiment;

FIG. 13 illustrates a schematic block diagram for calls between anetwork orchestrator, application, and hardware accelerator, accordingto at least one embodiment;

FIG. 14 illustrates a schematic block diagram for calls between anetwork orchestrator, multiple applications, and accelerator runningvirtual devices, according to at least one embodiment;

FIG. 15A illustrates a process flow diagram for abstracted transport ofinformation between two computing resources, according to at least oneembodiment;

FIG. 15B illustrates a table of transport abstraction APIs andassociated reference counts, according to at least one embodiment;

FIG. 16 illustrates an example data center system, according to at leastone embodiment;

FIG. 17A illustrates an example of an autonomous vehicle, according toat least one embodiment;

FIG. 17B illustrates an example of camera locations and fields of viewfor the autonomous vehicle of FIG. 17A, according to at least oneembodiment;

FIG. 17C is a block diagram illustrating an example system architecturefor the autonomous vehicle of FIG. 17A, according to at least oneembodiment;

FIG. 17D is a diagram illustrating a system for communication betweencloud-based server(s) and the autonomous vehicle of FIG. 17A, accordingto at least one embodiment;

FIG. 18 is a block diagram illustrating a computer system, according toat least one embodiment;

FIG. 19 is a block diagram illustrating computer system, according to atleast one embodiment;

FIG. 20 illustrates a computer system, according to at least oneembodiment;

FIG. 21 illustrates a computer system, according at least oneembodiment;

FIG. 22A illustrates a computer system, according to at least oneembodiment;

FIG. 22B illustrates a computer system, according to at least oneembodiment;

FIG. 22C illustrates a computer system, according to at least oneembodiment;

FIG. 22D illustrates a computer system, according to at least oneembodiment;

FIGS. 22E and 22F illustrate a shared programming model, according to atleast one embodiment;

FIG. 23 illustrates exemplary integrated circuits and associatedgraphics processors, according to at least one embodiment;

FIGS. 24A and 24B illustrate exemplary integrated circuits andassociated graphics processors, according to at least one embodiment;

FIGS. 25A and 25B illustrate additional exemplary graphics processorlogic according to at least one embodiment;

FIG. 26 illustrates a computer system, according to at least oneembodiment;

FIG. 27A illustrates a parallel processor, according to at least oneembodiment;

FIG. 27B illustrates a partition unit, according to at least oneembodiment;

FIG. 27C illustrates a processing cluster, according to at least oneembodiment;

FIG. 27D illustrates a graphics multiprocessor, according to at leastone embodiment;

FIG. 28 illustrates a multi-graphics processing unit (GPU) system,according to at least one embodiment;

FIG. 29 illustrates a graphics processor, according to at least oneembodiment;

FIG. 30 is a block diagram illustrating a processor micro-architecturefor a processor, according to at least one embodiment;

FIG. 31 illustrates at least portions of a graphics processor, accordingto one or more embodiments;

FIG. 32 illustrates at least portions of a graphics processor, accordingto one or more embodiments;

FIG. 33 illustrates at least portions of a graphics processor, accordingto one or more embodiments;

FIG. 34 is a block diagram of a graphics processing engine of a graphicsprocessor in accordance with at least one embodiment;

FIG. 35 is a block diagram of at least portions of a graphics processorcore, according to at least one embodiment;

FIGS. 36A and 36B illustrate thread execution logic including an arrayof processing elements of a graphics processor core according to atleast one embodiment;

FIG. 37 illustrates a parallel processing unit (“PPU”), according to atleast one embodiment;

FIG. 38 illustrates a general processing cluster (“GPC”), according toat least one embodiment;

FIG. 39 illustrates a memory partition unit of a parallel processingunit (“PPU”), according to at least one embodiment;

FIG. 40 illustrates a streaming multi-processor, according to at leastone embodiment;

FIG. 41 illustrates a network for communicating data within a 5Gwireless communications network, according to at least one embodiment;

FIG. 42 illustrates a network architecture for a 5G LTE wirelessnetwork, according to at least one embodiment;

FIG. 43 is a diagram illustrating some basic functionality of a mobiletelecommunications network/system operating in accordance with LTE and5G principles, according to at least one embodiment;

FIG. 44 illustrates a radio access network which may be part of a 5Gnetwork architecture, according to at least one embodiment;

FIG. 45 provides an example illustration of a 5G mobile communicationssystem in which a plurality of different types of devices is used,according to at least one embodiment;

FIG. 46 illustrates an example high level system, according to at leastone embodiment;

FIG. 47 illustrates an architecture of a system of a network, accordingto at least one embodiment;

FIG. 48 illustrates example components of a device, according to atleast one embodiment;

FIG. 49 illustrates example interfaces of baseband circuitry, accordingto at least one embodiment;

FIG. 50 illustrates an example of an uplink channel, according to atleast one embodiment;

FIG. 51 illustrates an architecture of a system of a network, accordingto at least one embodiment;

FIG. 52 illustrates a control plane protocol stack, according to atleast one embodiment;

FIG. 53 illustrates a user plane protocol stack, according to at leastone embodiment;

FIG. 54 illustrates components of a core network, according to at leastone embodiment; and

FIG. 55 illustrates components of a system to support network functionvirtualization (NFV), according to at least one embodiment.

DETAILED DESCRIPTION

Numerous specific details are set forth to provide a more thoroughunderstanding of at least one embodiment. However, it will be apparentto a skilled person that these inventive concepts may be practicedwithout one or more of these specific details and that aspects of one ormore embodiments described herein can be combined.

In at least one embodiment, in open radio access network (“0-RAN”)deployment, one or more central processing units (“CPUs”) processfunctional operations that are part of a Distributed Unit (“DU”) or acentralized unit (“CU”). In at least one embodiment, in O-RANdeployment, one or more CPUs can offload operations forcompute-intensive algorithms such as physical layer signal processing,gaming processing, and video processing to hardware accelerators in alower layer of an O-RAN network protocol stack. In at least oneembodiment, hardware accelerators can be a GPU, field programmable gatearray (“FPGA”), application specific integrated circuit (“ASIC”), systemon chip (“SoC”), or another processor specialized to accelerateprocessing (e.g., data processing units (DPUs), PPUs). In at least oneembodiment, hardware accelerators provide a performance boost toprocessing operations in O-RAN because they are designed to accelerateprocessing. For example, a GPU can perform thousands of operations inparallel as compared to a CPU that performs operations serially. Whilewireless radio networks such as 5G are used for the purpose ofillustration herein, any one or more aspects of any embodimentsdescribed herein may be used in any other suitable computer models,architectures, frameworks, protocols, and/or networks.

In at least one embodiment, 5G-NR service providers use 0-RAN to providea range of services. In at least one embodiment, hardware acceleratorscan have different capabilities for processing different types of 5G-NRworkloads, e.g., for processing workloads in different network slicesthat have different quality of service (QoS) requirements. In at leastone embodiment, different hardware accelerators may be used fordifferent purposes. For example, a particular GPU or group of GPUs mayinherently be better for performing a massive Machine-TypeCommunications (mMTC) workload related to gaming than a CPU because ofparallel processing architecture; as another example, a FPGA or groupFPGAs programmed for low latency workloads may be better at performing aURLLC workload to meet a QoS requirement as compared to a CPU because ofprogramming design to reduce latency in said FPGA or group of FPGA.Different hardware accelerators may use different communication ortransport protocols.

In at least one embodiment, an application deployed on an O-RAN networkmay not receive or have access to information about whether hardwareaccelerators in a lower layer (e.g., layer 1) support a transportprotocol also supported by said application. To account for differencesin transport protocols used between hardware accelerators andapplications, in at least one embodiment, apparatuses, systems, andtechniques perform one or more APIs that communicate data between alayer 2 (“L2”) and a layer 1 (“L1”) of an O-RAN network protocol stackwithout any modifications required to an application in L2. In at leastone embodiment, said one or more APIs can be performed by one or moreprocessors, as described below, to exchange information between L2 andL1 of an O-RAN network protocol stack despite differences in transportprotocols associated with L2 and L1.

FIG. 1 is a schematic overview block diagram for a network protocolstack 100, in accordance with at least one embodiment. In at least oneembodiment, network protocol stack 100 corresponds to or is to performone or more operations for 0-RAN network or other network protocol stackthat is to provide 5G-NR service, in other embodiments, network protocolstack 100 corresponds to providing sixth generation (6G) new radionetwork service or another wireless communication protocol stack (e.g.,any 3rd Generation partnership Project (3GPP) wireless communicationstandard). In at least one embodiment, network protocol stack 100 isused to support networks described in conjunction with at least FIG. 47.

FIG. 1 includes network protocol stack 100, application 105, layer 2(“L2”) or higher layer 110 (also referred to as “L2+”), layer 2 to layer1 interface 115 (also referred to as a “L2-L1 interface”), transportabstraction layer 117, drivers 120, first processor 125, secondprocessor 130, and network interface controller 135. In at least oneembodiment, L2 relates to a data link layer for 5G-NR that isresponsible for scheduling functions related to 5G-NR workloads. In atleast one embodiment, layer 1 (“L1”) refers to a physical layer of RANprotocol stack, which can be implemented as an L1 software libraryrunning on a first processor 125 (e.g., a CPU) and/or a second processor130 (e.g., an accelerated L1 run by an FPGA, GPU, ASIC, or a SoC). In atleast one embodiment, a layer refers to an abstraction of hardware thatperforms functions or operations for a system, network, or computer,e.g., L2 is an abstraction of hardware that performs data link andscheduling operations for an O-RAN network, and L1 is an abstraction ofreal time hardware that performs physical layer operations for an O-RANnetwork (e.g., O-RAN network). For example, layers correspond to OpenSystems Interconnection (OSI) model (e.g., L1, L2, L3) exposed by one ormore interfaces to handle functions or operations for 5G-NR.

In at least one embodiment, transport abstraction layer 115 of a 5G-NRnetwork protocol stack is located between a layer 1 (L1) and a layer 2plus (L2+), includes one or more application programming interfaces(APIs), and abstracts transports associated with L2+ so that softwareand/or hardware associated with L1 can respond to requests from L2+regardless of which type of transport protocol or informationtransmission types (e.g., Peripheral Component Interconnect Express(PCIe), shared memory, User Datagram Protocol (UDP)) are being used bywith L2+. In at least one embodiment, abstraction includes a mapping ofone set of functions to corresponding functions included in multipletransport protocols. In at least one embodiment, an informationtransmission type includes one or more information transmission typesused within a transport to communicate information between two 5G-NRcomputing resources. In at least one embodiment, a first informationtransmission type and a second information transmission type correspondto different messages carried through one transport, and one or moreassociated buffer allocations occur with different processes and/ordevices, for example, a first transmission type has correspondingbuffers allocated from a buffer pool in a CPU and a second transmissiontype has corresponding buffers allocated in a hardware accelerator(e.g., GPU), wherein said first information transmission typecorresponds to control plane messages and said second informationtransmission type corresponds to user plane (e.g. transport block)messages. In at least one embodiment, both first and second informationtransmission types are control plane messages, user plane data, or somecombination thereof, mapped to different transport types.

In at least one embodiment, application 105 is a RAN protocol stackprogram running on a host CPU (e.g., first processor 125). For example,application 105 relates to software for a service provider of 5G-NR toprovide eMBB, URLLC, mMTC, and/or V2X for one or several cells in a5G-NR network. While one application 105 is shown in FIG. 1 , severalapplications can be run on network protocol stack 100, where eachapplication 105 provides identical or different services.

In at least one embodiment, L2-L1 interface 115 enables application 105to communicate with L1 and to cause drivers 120 in L1 to control firstprocessor 125, second processor 130, and network interface controller135. In at least one embodiment, an application 105 uses L2-L1 interface115 and one or more APIs to determine how many 5G-NR cells can besupported concurrently be L1 resources (e.g., hardware accelerators),scheduling or prioritizing workloads that are processed by L1 resourcesand performing operations to reconfigure or update L1 resources astraffic conditions change in a 5G-NR network. In at least oneembodiment, L2-L1 interface 115 is an interface such as a 5^(th)Generation Functional Application Programming Interface (5G FAPI),and/or variations thereof. In at least one embodiment, L2-L1 interface115 communicates with an acceleration abstraction layer (AAL) interface.

In at least one embodiment, network protocol stack 100 includestransport abstraction layer 117, which is described further herein,including in conjunction with at least FIGS. 2-15 . In at least oneembodiment, transport abstraction layer 117 exists between L2-L1interface 115 and drivers 120. In at least one embodiment, transportabstraction layer 117 exists between L2+ and L1. In at least oneembodiment, transport abstraction layer 117 includes one or moretransport abstraction APIs and one or more transport abstractionimplementors. In at least one embodiment, transport abstraction layer117 exists below drivers 120. In at least one embodiment, L2-L1interface 115 includes transport abstraction layer 117. In at least oneembodiment, transport abstraction layer 117 allows a RAN applicationfrom one vendor to transport data to and/or from a hardware and/orsoftware component from another vendor without said RAN applicationhaving information about which transport configurations said componentsupports, for example, using transport abstraction layer 117, a RANapplication in L2+ can communicate with L1 software that supports ashared memory based transport and communicate with another L1 softwarethat supports PCIe interconnect based transport.

In at least one embodiment, drivers 120 include libraries to operatefirst processor 125, second processor 130, and network interfacecontroller 135. In at least one embodiment, a driver, also referred toas a device driver, is a computer program that operates, controls, orotherwise provides an interface with various hardware, such as hardwareaccelerator devices and network communication/interface devices. In atleast one embodiment, drivers 120 comprise one or more functions,processes, libraries, interfaces, and/or variations thereof that providesupport for L2-L1 interface 115. In at least one embodiment, drivers 120are implemented such that functions of L2-L1 interface 115 can beappropriately processed in connection with first processor 125, secondprocessor 130, and network interface controller 135.

In at least one embodiment, first processor 125 is a processor that hasone or more circuits to perform operations corresponding to networkprotocol stack 100. For example, first processor 125 is a CPU that isconfigured to perform or operation a DU or CU for a O-RAN. In at leastone embodiment, second processor 130 is a hardware accelerator. Hardwareaccelerators can be graphics processing units (GPUs), field programmablegate arrays (FPGAs), application specific integrated circuits (ASICs),system on chip (SoC), or other processors specialized to improveperformance processing (e.g., parallel processing units). In at leastone embodiment, first processor 125 (e.g., CPU running a DU in an O-RANnetwork) can offload operations for compute-intensive algorithms such asphysical (PHY) layer signal processing, gaming related processing, videoprocessing, and crypto processing to second processor 130 (e.g.,hardware accelerators).

In at least one embodiment, a network interface controller (NIC) 135 isa hardware component that connects one or more computing systems to oneor more computing networks. In at least one embodiment, NIC 135 receivesdata to be processed by first processor 125 or second processor 130(e.g., a hardware accelerator) and transmits data processed by firstprocessor 125 or second processor 130 to another component in an O-RANnetwork (e.g., base station). In at least one embodiment, NIC 135receives data to be processed through one or more functions ofacceleration abstraction layer interface (e.g., a transport abstractionlayer interface) and transmits data processed through one or morefunctions of acceleration abstraction layer interface. In at least oneembodiment, NIC 135 interacts with a remote radio head (RRH), alsoreferred to as a remote radio unit (RRU) as part of providing 5G-NRservice. One or more aspects of one or more embodiments described inconjunction with FIG. 1 can be combined with one or more aspects of oneor more embodiments described in conjunction with FIGS. 2-15 .

FIG. 2 illustrates transport abstraction framework 200, according to atleast one embodiment. In at least one embodiment, transport abstractionframework 200 includes L2+ 210, L1 212, transport abstraction layer 217,transport abstraction APIs 219, application processes 220, accelerationprocesses 222, transport abstraction APIs 219, transport abstractionimplementor 230, shared memory protocol information 232, Data PlaneDevelopment Kit (DPDK) framework information 234, and User DatagramProtocol (UDP) socket protocol information 236. In at least oneembodiment, transport abstraction APIs 219 are a unified set oftransport abstraction APIs. In at least one embodiment, each transportabstraction API 219 is associated with different types of transportprotocols supported by 5G-NR computing resources (e.g., hardwareaccelerators). In at least one embodiment, transport refers to a methodand/or protocol for sending data from one computing resource to another.In at least one embodiment, computing resources can support a transportprotocol, and when a computing resource is configured to support saidtransport protocol, said computing resource is referred to as having atransport configuration. In at least one embodiment, transportabstraction framework 200 is used, at least in part, to transfer databetween disaggregated 5G-NR computing resources. In at least oneembodiment, disaggregated 5G-NR computing resources are physicallylocated in one system, for example, an application on a computer may bedisaggregated from a CPU on said computer because said CPU supports aPCIe card interface that said application does not support. In at leastone embodiment, disaggregated 5G-NR computing resources are physicallydisaggregated by geographic location. In at least one embodiment,disaggregated computing resources include computing resources that arephysically separated. In at least one embodiment, disaggregatedcomputing resources include computing resources that are communicativelyconnected. In at least one embodiment, disaggregated computing resourcesinclude computing resources that are communicatively separated unlessmodified, (e.g., incompatible without modification, unable to performinteroperably without modification). In at least one embodiment, eachtransport abstraction API 219 is regarded conceptually to map todifferent types of transport protocols. In at least one embodiment, atransport abstraction framework 200 is regarded conceptually to abstracttransport protocol variations based, at least in part, on transportabstraction APIs 219. In at least one embodiment, transport abstractionframework 200 allows application processes 220 associated with L2+ 210to interact with L1 212 and transport data to and from L1 212 usingtransport abstraction APIs 219, regardless of which transport protocol(e.g., PCIe, shared memory, UDP) L1 212 supports. In at least oneembodiment, transport abstraction framework 200 abstracts applicationprocesses 220 in L2+ 210 from various L1 212 transport implementations,without requiring any modification to code associated with applicationprocesses 220.

In at least one embodiment, transport abstraction APIs 219 include fiveAPIs—buffer_alloc( ), buffer_clone( ), buffer_send( ), buffer_release(), and buffer_recv( ). In at least one embodiment, one or more circuitsof a processor perform an API (e.g., buffer_alloc( )) to select storage(e.g., memory) to be used to transfer information between a plurality of5G-NR computing resources. As used herein, a “buffer” includes one ormore buffers. In at least one embodiment, a buffer is a ring buffer,although it can be another type of buffer. In at least one embodiment,an application calls buffer_alloc( ) and in response, transportabstraction implementor 230 allocates said application's requestedbuffer from a pre-configured buffer pool and sends said buffer to saidapplication to transmit data from application to transport abstractionimplementor 230. In at least one embodiment, buffer_alloc( ) initializesa reference counter and sets said reference counter to one (e.g.,ref_count=1). In at least one embodiment, a reference counterinitialized by buffer_alloc( ) is used to identify when to deallocate orrelease an allocated buffer. In at least one embodiment, an applicationcalls buffer_alloc( ) to assign a buffer.

In at least one embodiment, one or more circuits of a processor performan API (e.g., buffer_clone( ), buffer_retain( )) to prevent deselectionof storage selected to be used to transfer information between aplurality of 5G-NR computing resources. In at least one embodiment, anapplication optionally calls buffer_clone( ) when said application isconfigured to retain a buffer instead of having transport abstractionimplementor 230 release said buffer. In at least one embodiment,buffer_clone( ) increments a reference counter associated with anallocated buffer, for example, if a reference counter held a value of 1prior to invoking buffer_clone( ), then performing buffer_clone( )increments said reference counter to hold a value of two (e.g.,ref_count=2).

In at least one embodiment, one or more circuits of a processor performsan API (e.g., buffer_send( )) to cause data to be stored in storageselected to be used to transfer information between a plurality of 5G-NRcomputing resources. In at least one embodiment, an application callsbuffer_send( ) after data is populated to a buffer assigned bybuffer_alloc( ) and in response, buffer_send( ) causes transportabstraction implementor 230 to send said data. In at least oneembodiment, buffer_send( ) causes transport abstraction implementor todecrement a reference counter by one for example, if transportabstraction implementor 230 decrements a reference counter to zero(e.g., ref_count=0) in response to buffer_send( ), then transportabstraction implementor 230 releases an allocated buffer. In at leastone embodiment, buffer_send( ) is implemented as an asynchronous (ornon-blocking) or synchronous (or blocking) API, for example, ifbuffer_send( ) is being implemented as an asynchronous API or within anasynchronous mode, an application (or application thread) invokingbuffer_send( ) will not be blocked and wait for an API call response;said application thread can later query a status of the buffer_send( )API with a query such as buffer_status_query( ). In another example,wherein buffer_send is implemented as a synchronous API or with asynchronous mode, an application (or application thread) callingbuffer_send( ) could be blocked unless a transport abstractionimplementor provides a call back confirming said buffer has beensuccessfully sent, which does not require invocation of abuffer_status_query( ) said application.

In at least one embodiment, when an application invokes buffer_release(), a transfer of buffer ownership (or to whom a buffer is assigned)occurs from said application to a transport abstraction implementor. Inat least one embodiment, a buffer transferred from an application to atransport abstraction implementor does not immediately release saidbuffer by said transport abstraction implementor; said transportabstraction implementor will release said buffer if before saidapplication invokes buffer_release( ) said transport abstractionimplementor has completed an operation caused by buffer_send( ) such assending said buffer; however, if a buffer transmission is still ongoing,said transport implementor will not immediately release said buffer andwill release said buffer after said transmission is complete. In atleast one embodiment, a separate buffer_release( ) call abstracted froman application is internal to or coming from a transport abstractionimplementor, wherein, for example, a reference counter will be adjustedaccordingly so that said reference counter will reach 0 only when bothsaid as well as said transport abstraction implementor have separatelyinvoked buffer_release( ).

In at least one embodiment, one or more circuits of a processor performsan API (e.g., buffer_release( ) to deselect storage selected to be usedto transfer information between a plurality of 5G-NR computingresources. In at least one embodiment, an application callsbuffer_release( ) to cause transport abstraction implementor 230 todecrement a reference counter, for example, if transport abstractionimplementor 230 decrements a reference counter to zero (e.g.,ref_count=0) in response to buffer_release( ), then transportabstraction implementor 230 releases an allocated buffer.

In at least one embodiment, one or more circuits of a processor performsan API (e.g., buffer_recv( )) to obtain data from storage selected to beused to transfer information between a plurality of 5G-NR computingresources. In at least one embodiment, an application calls buffer_recv() to cause transport abstraction implementor 230 to allocate a bufferand populate said buffer with data requested by said application,wherein said data is to be transferred to said application. In at leastone embodiment, when transport abstraction implementor 230 allocates abuffer in response to buffer_recv( ), a reference counter is set to avalue of one and is not decremented with buffer_recv( ). In at least oneembodiment, an application calls buffer_release( ) after invokingbuffer_recv( ) to release an allocated buffer into a buffer pool.

In at least one embodiment, application processes 220 include processesfrom applications implemented in L2+ 210. In at least one embodiment,application processes 220 include processes related to applications thatuse RAN architecture due to disaggregated computing resources, forexample, applications implemented in a vehicle used to provide drivingassistance (e.g., sign detection, obstacle detection, navigation) andrequiring wireless access to hardware accelerators and/or databases. Inat least one embodiment, acceleration processes 222 include processesperformed by accelerators based in hardware and/or software. In at leastone embodiment, acceleration processes 222 include processes performedby hardware accelerators such as GPUs, FPGAs, and ASICs.

In at least one embodiment, transport abstraction implementor 230 isinstalled, at least in part, on a 5G-NR computing resource. In at leastone embodiment, transport abstraction implementor 230 is installed, atleast in part on a hardware accelerator. In at least one embodiment,transport implementor 230 is located in L1 of a 5G-NR network protocolstack. In at least one embodiment, transport abstraction implementor 230includes libraries, drivers, mappings between transport protocols, orsome combination thereof. In at least one embodiment, transportabstraction implementor is installed, at least in part, on a host CPU ina 5G-NR network. In at least one embodiment, transport abstractionimplementor 230 includes any combination of hardware and/or softwarerequired to allow one or more 5G-NR computing resources associated witha first transport profile to transfer data to and/or from one or moreother 5G-NR computing resources associated with a second transportprofile. In at least one embodiment, transport abstraction implementor230 is an application.

In at least one embodiment, transport abstraction implementor 230, (alsoreferred to as a transport abstraction API implementor) includes sharedmemory protocol information 232, DPDK library 234, and UDP socketprotocol information 236. In at least one embodiment, protocolinformation includes libraries, drivers, protocols, applications, orsome combination thereof. In at least one embodiment, shared memorylibrary 232 includes drivers, functions, operations, protocols,routines, programs, code, or some combination thereof, used, at least inpart, to execute a transport of data using shared memory. In at leastone embodiment, shared memory is located on a hardware accelerator suchas a GPU. In at least one embodiment, DPDK library 234 includes drivers,functions, operations, protocols, routines, programs, code, or somecombination thereof, used, at least in part, to execute a transportimplementation based on DPDK. In at least one embodiment, UDP socketprotocol information 236 includes drivers, functions, operations,protocols, routines, programs, code, or some combination thereof, used,at least in part, to execute a transport implementation based on socketcalls. In at least one embodiment, when an application calls a transportabstraction API 219, said API is sent to transport abstractionimplementor 230. In at least one embodiment, transport abstractionimplementor 230 includes a mapping or set of associations between one ormore transport abstraction APIs 219 and one or more operations relatedto shared memory protocol information 232, DPDK library 234, UDP socketprotocol information 236, or some combination thereof. In at least oneembodiment, transport abstraction implementor 230 causes a hardwareand/or software accelerator to perform an operation associated with atransport profile in response to, at least in part, a transportabstraction API 219 being called by an application that uses a differenttransport implementation. One or more aspects of one or more embodimentsdescribed in conjunction with FIG. 2 can be combined with one or moreaspects of one or more embodiments described in conjunction with FIGS. 1and 3-15 .

FIG. 3 illustrates a schematic block diagram for a flow 300 fortransmission of data with transport abstraction, in accordance with atleast one embodiment. In at least one embodiment, moving from top tobottom in flow 300 indicates a progression of time. Flow 300 and itsblocks, which represent one or more operations, are not illustrated toscale. In at least one embodiment flow 300 illustrates, at least inpart, transfer of data using non-zero copy techniques. In at least oneembodiment, non-zero copy techniques include application 320 copyingdata into a newly-allocated buffer (e.g., using a memcopy function)instead of using a buffer previously allocated and used by saidapplication. In at least one embodiment, flow 300 shares techniquesdescribed herein and at least in conjunction with FIGS. 4-14 . In atleast one embodiment, flow 300 includes application 320, transportabstraction API implementor 330, buffer_allocate( ) API 350, andbuffer_send( ) API 352. In at least one embodiment, flow 300 begins withapplication calling buffer_allocate( ) API 350. In at least oneembodiment, in response to application 320 calling buffer_allocate( )API 350, transport abstraction API implementor 330 allocates a buffer,returns said buffer (e.g., buffer identification (buffer id)), andinitializes a reference counter 360 as described herein and at least inconjunction with FIG. 2 . In at least one embodiment, when application320 receives buffer from transport abstraction API implementor,application 320 copies data in said buffer 342. In at least oneembodiment, application calls buffer_send( ) API 352 to send data copiedin an allocated buffer. In at least one embodiment, in response toapplication 320 calling buffer_send( ) API 352, transport abstractionAPI implementor 330 sends data over a transport, decrements a referencecounter by one, and releases an allocated buffer back into a buffer pool362. In at least one embodiment, application 320 initiates aretransmission 344 with transport abstraction API implementor 330 bycalling buffer_allocate( ) API 350, which results in a buffer beingallocated from a pre-created pool, returning said allocated buffer tosaid application, and incrementing a reference counter by one 364. In atleast one embodiment, in response to receiving a buffer, application 320copies data in said buffer 346 and calls buffer_send( ) API 352, whichcauses transport abstraction API implementor to send data over atransport, decrement a reference counter by one, and release anallocated buffer back to a buffer pool 366. In at least one embodiment,flow 300 includes one or more blocks between those illustrated in FIG. 3. One or more aspects of one or more embodiments described inconjunction with FIG. 3 can be combined with one or more aspects of oneor more embodiments described in conjunction with FIGS. 1-2 and 4-15 .

FIG. 4 illustrates a schematic block diagram for a flow 400 fortransmission of data with transport abstraction, in accordance with atleast one embodiment. In at least one embodiment, moving from top tobottom in flow 400 indicates a progression of time. Flow 400 and itsblocks are not illustrated to scale. In at least one embodiment, flow400 illustrates, at least in part, transfer of data using zero copytechniques. In at least one embodiment, zero copy techniques includeapplication 420 retaining a buffer instead of using memcopy duringretransmission. In at least one embodiment, flow 400 shares techniquesdescribed herein and at least in conjunction with FIGS. 3 and 5-14 . Inat least one embodiment, flow 400 includes application 420, transportabstraction API implementor 430, buffer_allocate( ) API 450, buffer_sendAPI 452, buffer_clone( ) API 454, and buffer_release API 458. In atleast one embodiment, in response to application 420 callingbuffer_allocate( ) API 450, transport abstraction API implementor 430allocates a buffer, returns said buffer, and initializes referencecounter 460 as described herein and at least in conjunction with FIG. 2. In at least one embodiment, flow 400 includes buffer_clone( ) API 454that retains a buffer allocated by buffer_allocate( ) API 450, which isdescribed herein at least in conjunction with FIG. 2 . In at least oneembodiment, a user or separate application configures application 420 toimplement zero copy techniques, and therefore, application 420 callsbuffer_clone( ) API 454. In at least one embodiment, buffer_clone( ) APIobviates a requirement to re-allocate a buffer for retransmission by anapplication. In at least one embodiment, buffer_clone( ) API 454increments a reference counter 462 to prevent a buffer from beingdeallocated after application 420 calls buffer_send( ) API 452. In atleast one embodiment, buffer_clone( ) increments a reference counter to2 so after buffer_send( ) API 452 decrements a reference counter to 1,an allocated buffer is not deallocated. In at least one embodimentapplication 420 populates data in a buffer 442 duplicated bybuffer_clone API 454. In at least one embodiment, application 420 callsbuffer_send API 452 following data population 442, which causestransport abstraction API implementor 430 to send said data over atransport and decrement a reference counter by one 464. In at least oneembodiment, after transport abstraction API implementor 430 sends dataover a transport, application 420 initiates a retransmission 444 bycalling buffer_clone API 454. In at least one embodiment, buffer_sendAPI 452 causes transport abstraction API implementor 430 to send data468 from a buffer duplicated earlier by buffer_clone API 454. In atleast one embodiment, application 420 calls buffer_release( ) API 458 todeallocate or release a buffer 446. In at least one embodiment,buffer_release( ) API 458 decrements a reference counter by 1, causingsaid reference counter to hold a value of zero and causing transportabstraction API implementor 430 to return a buffer back to a buffer pool470. In at least one embodiment, flow 400 includes one or more blocksbetween those illustrated in FIG. 4 . One or more aspects of one or moreembodiments described in conjunction with FIG. 4 can be combined withone or more aspects of one or more embodiments described in conjunctionwith FIGS. 1-3 and 5-15 .

FIG. 5 illustrates a schematic block diagram for a flow 400 fortransmission of data with transport abstraction, in accordance with atleast one embodiment. In at least one embodiment, moving from top tobottom in flow 500 indicates a progression of time. Flow 500 and itsblocks are not illustrated to scale. In at least one embodiment, flow500 illustrates, at least in part, transfer of data using zero copytechniques without any automatic buffer release. In at least oneembodiment, zero copy techniques include application 520 retaining abuffer instead of using memcopy during retransmission. In at least oneembodiment, flow 500 does not release a buffer unless application 520calls buffer_release API 558. In at least one embodiment, flow 500shares techniques described herein and at least in conjunction withFIGS. 3-4 and 6-14 . In at least one embodiment, flow 500 includesapplication 520, transport abstraction API implementor 530,buffer_allocate( ) API 550, buffer_send API 552, and buffer_release API558. In at least one embodiment, in response to application 420 callingbuffer_allocate( ) API 550, transport abstraction API implementor 530allocates a buffer, returns said buffer, and initializes a referencecounter 560 as described herein and at least in conjunction with FIG. 2. In at least one embodiment, when application 520 receives buffer fromtransport abstraction API implementor, application 520 copies data insaid buffer 542. In at least one embodiment, application callsbuffer_send( ) API 552 to send data copied in an allocated buffer. In atleast one embodiment, in response to application 520 callingbuffer_send( ) API 552, transport abstraction API implementor 530 sendsdata over a transport 562, without decrementing a reference counter, andthereby does not release an allocated buffer back into a buffer pool. Inat least one embodiment, application 520 initiates a retransmission 544with transport abstraction API implementor 530 by calling anotherbuffer_send( ) API 552 without decrementing a reference counter. In atleast one embodiment, after buffer_send( ) API 552 causes transportabstraction API implementor 530 to send data 564 over a transport,application 520 requests a release of a buffer 546 by callingbuffer_release( ) API 558. In at least one embodiment, buffer_release( )API 558 decrements a reference counter by 1, causing said referencecounter to hold a value of zero and causing transport abstraction APIimplementor 530 to return a buffer back to a buffer pool 566. In atleast one embodiment, flow 500 includes one or more blocks between thoseillustrated in FIG. 5 . One or more aspects of one or more embodimentsdescribed in conjunction with FIG. 5 can be combined with one or moreaspects of one or more embodiments described in conjunction with FIGS.1-4 and 6-15 .

FIG. 6 illustrates a schematic block diagram for a flow 600 forreceiving data with transport abstraction, in accordance with at leastone embodiment. In at least one embodiment, flow 600 illustrates, atleast in at part, transfer of data using non-zero copy techniques. In atleast one embodiment, moving from top to bottom in flow 600 indicates aprogression of time. Flow 600 and its blocks, which represent one ormore operations, are not illustrated to scale. In at least oneembodiment, flow 600 includes an application 620 that has its own copyof a buffer for reassembly. In at least one embodiment, reassemblyrefers to a reassembly of fragmented IP packets, for example, when apacket size exceeds a maximum transmission unit (MTU) of Ethernet. In atleast one embodiment, reassembly in a shared memory context refers toscatter and gather operations, for example, operations used whentransport blocks (TBs) are stored in non-contiguous buffers in memory.In at least one embodiment, non-zero copy techniques include anapplication 620 copying data into a buffer (e.g., using a memcopyfunction) assigned to application 620. In at least one embodiment, flow600 shares techniques described herein and at least in conjunction withFIGS. 3-5 and 7-14 . In at least one embodiment, flow 600 includesapplication 620, transport abstraction API implementor 630,buffer_allocate( ) API 650, buffer_recv( ) API 656, and buffer_releaseAPI 658. In at least one embodiment, in response to application 620calling buffer_allocate( ) API 650, transport abstraction APIimplementor 630 allocates a buffer, returns said buffer, and initializesa reference counter 660 as described herein and at least in conjunctionwith FIG. 2 . In at least one embodiment, after application 620 callsbuffer_allocate( ) API 650, application calls buffer_recv( ) API 656,which causes transport abstraction API implementor 630 to receive data662 into an allocated buffer and does not increment or decrement areference counter 660. In at least one embodiment, application 620performs a memcopy function to said application's own buffer 640. In atleast one embodiment, after application 620 performs memcopy operation640, application 620 initiates a release 642 of an allocated buffer 641by calling buffer_release( ) API 658, which causes transport abstractionAPI implementor 630 to decrement a reference counter by one so saidreference counter holds a value of zero, which returns said allocatedbuffer to a buffer pool 664. In at least one embodiment, flow 600includes one or more blocks between those illustrated in FIG. 6 . One ormore aspects of one or more embodiments described in conjunction withFIG. 6 can be combined with one or more aspects of one or moreembodiments described in conjunction with FIGS. 1-5 and 7-15 .

FIG. 7 illustrates a schematic block diagram for a flow 700 forreceiving data with transport abstraction, in accordance with at leastone embodiment. In at least one embodiment, flow 700 illustrates, atleast in at part, transfer of data using zero copy techniques. In atleast one embodiment, moving from top to bottom in flow 700 indicates aprogression of time. Flow 700 and its blocks, which represent one ormore operations, are not illustrated to scale. In at least oneembodiment, flow 700 includes an application 720 that retains a bufferfor reassembly. In at least one embodiment, flow 700 shares techniquesdescribed herein and at least in conjunction with FIGS. 3-6 and 8-14 .In at least one embodiment, flow 700 includes application 720, transportabstraction API implementor 730, buffer_allocate( ) API 750,buffer_recv( ) API 757, and buffer_release API 758. In at least oneembodiment, in response to application 720 calling buffer_allocate( )API 750, transport abstraction API implementor 730 allocates a buffer,returns said buffer, and initializes a reference counter 760 asdescribed herein and at least in conjunction with FIG. 2 . In at leastone embodiment, after application 720 calls buffer_allocate( ) API 750,application calls buffer_recv( ) API 756, which causes transportabstraction API implementor 730 to receive data into an allocated bufferand does not increment or decrement a reference counter 760. In at leastone embodiment, application 720 invokes buffer_allocate( ) API 750, forexample, application 720 receives a buffer allocation. In at least oneembodiment, transport abstraction API implementor 730 returns a bufferin response to a buffer_allocate( ) API 750 function call, and saidbuffer is passed by application 720 in a subsequent buffer_recv( ) API756.

In at least one embodiment, transport abstraction API implementor 730places received data in a buffer, if provided, 762 passed by application720 in a subsequent buffer_recv( ) API 756. In at least one embodiment,application 720 initiates a release 740 of an allocated buffer 741 bycalling buffer_release( ) API 758, which causes transport abstractionAPI implementor 730 to decrement a reference counter by one so saidreference counter holds a value of zero, which returns said allocatedbuffer to a buffer pool 764. In at least one embodiment, flow 700includes one or more blocks between those illustrated in FIG. 7 . One ormore aspects of one or more embodiments described in conjunction withFIG. 7 can be combined with one or more aspects of one or moreembodiments described in conjunction with FIGS. 1-6 and 8-15 .

FIG. 8 illustrates a schematic block diagram for a flow 800 forreceiving data with transport abstraction, in accordance with at leastone embodiment. In at least one embodiment, flow 800 illustrates, atleast in at part, transfer of data using non-zero copy techniques. In atleast one embodiment, moving from top to bottom in flow 800 indicates aprogression of time. Flow 800 and its blocks, which represent one ormore operations, are not illustrated to scale. In at least oneembodiment, flow 800 includes an application 820 that has its own copyof a buffer for reassembly. In at least one embodiment, non-zero copytechniques include an application 820 copying data into a buffer (e.g.,using a memcopy function) assigned to application 820. In at least oneembodiment, flow 800 shares techniques described herein and at least inconjunction with FIGS. 3-7 and 9-14 . In at least one embodiment, flow800 includes application 820, transport abstraction API implementor 830,buffer_recv( ) API 856, and buffer_release API 858. In at least oneembodiment, application calls buffer_recv( ) API 856, which causestransport abstraction API implementor 830 to receive data into anallocated buffer and increments a reference counter 860. In at least oneembodiment, application 820 performs a memcopy function to saidapplication's own buffer 840. In at least one embodiment, afterapplication 820 performs memcopy operation 840, application 820initiates a release 842 of an allocated buffer 841 by callingbuffer_release( ) API 858, which causes transport abstraction APIimplementor 830 to decrement a reference counter by one so saidreference counter holds a value of zero, which returns said allocatedbuffer to a buffer pool 862. In at least one embodiment, flow 800includes one or more blocks between those illustrated in FIG. 8 . One ormore aspects of one or more embodiments described in conjunction withFIG. 8 can be combined with one or more aspects of one or moreembodiments described in conjunction with FIGS. 1-7 and 9-15 .

FIG. 9 illustrates a schematic block diagram for a flow 900 forreceiving data with transport abstraction, in accordance with at leastone embodiment. In at least one embodiment, flow 900 illustrates, atleast in at part, transfer of data using zero copy techniques. In atleast one embodiment, moving from top to bottom in flow 900 indicates aprogression of time. Flow 900 and its blocks, which represent one ormore operations, are not illustrated to scale. In at least oneembodiment, flow 900 includes an application 920 that retains a bufferfor reassembly. In at least one embodiment, flow 900 shares techniquesdescribed herein and at least in conjunction with FIGS. 3-8 and 10-14 .In at least one embodiment, flow 900 includes application 920, transportabstraction API implementor 930, buffer_recv( ) API 956, andbuffer_release API 958. In at least one embodiment, application callsbuffer_recv( ) API 956, which causes transport abstraction APIimplementor 930 to receive data into an allocated buffer and incrementsa reference counter 960. In at least one embodiment, application 920initiates a release 940 of an allocated buffer 941 by callingbuffer_release( ) API 958, which causes transport abstraction APIimplementor 930 to decrement a reference counter by one so saidreference counter holds a value of zero, which returns said allocatedbuffer to a buffer pool 962. In at least one embodiment, flow 900includes one or more blocks between those illustrated in FIG. 9 . One ormore aspects of one or more embodiments described in conjunction withFIG. 9 can be combined with one or more aspects of one or moreembodiments described in conjunction with FIGS. 1-8 and 10-15 .

FIG. 10 illustrates a schematic block diagram 1000 representing amapping of transport abstraction APIs to a transport profile, accordingto at least one embodiment. In at least one embodiment, flow 1000includes application 1020, transport abstraction API implementor 1030,and transport configuration PCIe using DPDK 1070. In at least oneembodiment, block diagram 1000 includes buffer_allocate( ) API 1050,buffer_send( ) API 1052, buffer_recv( ) API 1056 and buffer_release( )API 1058. In at least one embodiment, block diagram 1000 includes PCIeoperations mbuff alloc 1072, enqueue and tx_burst 1074, mbuff free 1076,and dequeue and rx_burst 1078. In at least one embodiment, duringtransmission, for example, when an application 1020 calls transportabstraction API, transport abstraction API implementor 1030 mapsbuffer_allocate( ) API 1050 to mbuff alloc 1072, buffer_send( ) API 1052to enqueue and tx_burst 1074, and buffer_release( ) API 1058 to mbufffree 1076. In at least one embodiment, during reception, for example,when a buffer is received from an application 1020, buffer_allocate( )API 1050 maps to mbuff alloc 1072, buffer_recv( ) API 1056 maps todequeue and rx_burst 1078, and buffer_release( ) API 1058 maps to mbufffree 1076.

In at least one embodiment, as illustrated in flow 1000, application1020 calls transport abstraction APIs buffer_allocate( ), buffer_send(), buffer_release( ), and buffer_recv( ) during transmit and receiveoperations. In at least one embodiment, application 1020 is in L2+ andcalls transport abstraction APIs without information or knowledge of atransport profile associated with L1. In at least one embodiment, whenapplication 1020 calls a transport abstraction API, transportabstraction API implementor 1030 calls a corresponding function from alibrary associated with said transport profile, for example, whenapplication calls buffer_alloc( ) API 1050, transport abstraction APIimplementor 1030 calls a function from a DPDK library, mbuff alloc,which corresponds with buffer_alloc( ) API 1050. One or more aspects ofone or more embodiments described in conjunction with FIG. 10 can becombined with one or more aspects of one or more embodiments describedin conjunction with FIGS. 1-9 and 11-15 .

FIG. 11 illustrates a schematic block diagram 1100 representing amapping of transport abstraction APIs to a transport profile, accordingto at least one embodiment. In at least one embodiment, flow 1100includes application 1120, transport abstraction API implementor 1130,and transport configuration using shared memory 1170. In at least oneembodiment, block diagram 1100 includes buffer_allocate( ) API 1150,buffer_send( ) API 1152, buffer_recv( ) API 1156 and buffer_release( )API 1158. In at least one embodiment, block diagram 1100 includes sharedmemory operations allocate memory from pool 1172, enqueue buffer 1174,release memory to pool 1176, and dequeue buffer 1178. In at least oneembodiment, during transmission, for example, when a buffer is sent froman application 1120, transport abstraction API implementor 1130 mapsbuffer_allocate( ) API 1050 to allocate memory from pool 1172,buffer_send( ) API 1152 to enqueue buffer 1174, and buffer_release( )API 1158 to release memory to pool 1176. In at least one embodiment,during reception, for example, when a buffer is received from anapplication 1120, buffer_allocate( ) API 1150 maps to allocate memoryfrom pool 1172, buffer_recv( ) API 1152 maps to dequeue buffer 1178, andbuffer_release( ) API 1158 maps to release memory to pool 1176. One ormore aspects of one or more embodiments described in conjunction withFIG. 11 can be combined with one or more aspects of one or moreembodiments described in conjunction with FIGS. 1-10 and 12-15 .

FIG. 12 illustrates a schematic block diagram 1100 representing amapping of transport abstraction APIs to a transport profile, accordingto at least one embodiment. In at least one embodiment, flow 1200includes application 1220, transport abstraction API implementor 1230,and transport configuration using shared memory 1270. In at least oneembodiment, block diagram 1200 includes buffer_allocate( ) API 1250,buffer_send( ) API 1252, buffer_recv( ) API 1256 and buffer_release( )API 1258. In at least one embodiment, block diagram 1200 includes sharedmemory operations allocate memory from pool 1272, enqueue buffer 1274,release memory to pool 1276, and dequeue buffer 1278. In at least oneembodiment, during transmission, for example, when a buffer is sent froman application 1220, buffer_allocate( ) API 1050 maps to allocate memoryfrom pool 1272, buffer_send( ) API 1252 maps to socket send 1274, andbuffer_release( ) API 1258 maps to release memory to pool 1276. In atleast one embodiment, during reception, for example, when a buffer isreceived from an application 1220, buffer_allocate( ) API 1250 maps toallocate memory from pool 1272, buffer_recv( ) API 1252 maps to socketreceive 1278, and buffer_release( ) API 1258 maps to release memory topool 1276. One or more aspects of one or more embodiments described inconjunction with FIG. 12 can be combined with one or more aspects of oneor more embodiments described in conjunction with FIGS. 1-11 and 13-15 .

FIG. 13 illustrates a call flow diagram 1300 for calls between a networkorchestrator 1380, hardware accelerator 1390, and application 1320,according to at least one embodiment. In at least one embodiment,network orchestrator 1380 includes any computing component, device,and/or system, that manages flow of information within a 5G-NR network.In at least one embodiment, a network orchestrator is referred to as aservice management and orchestration (SMO) platform. In at least oneembodiment, network orchestrator 1380 manages flow of informationbetween layers of a 5G-NR network protocol stack. In at least oneembodiment, hardware accelerator 1390 includes any computing component,device, and/or system, that executes functions to process and/ortransfer information within a 5G-NR network. In at least one embodiment,hardware accelerator 1390 includes one or more device drivers 1392, oneor more libraries 1394, one or more hardware acceleration managers 1396,or some combination thereof. In at least one embodiment, diagram 1300begins with network orchestrator 1380 querying a hardware accelerator'scapabilities 1340, including which transport profiles hardwareaccelerator supports. In at least one embodiment, hardware accelerator1390 returns 1342 to network orchestrator 1380 information associatedwith its capabilities, including supported transport profiles. In atleast one embodiment, network orchestrator 1380 configures 1344 hardwareaccelerator 1390 with transport specific configurations for supportedtransport profile types. In at least one embodiment, hardwareaccelerator 1390 sends acknowledgement 1346 to network orchestrator 1380that hardware accelerator 1390 has been configured with transportspecific configurations for supported transport profile types. In atleast one embodiment, if hardware accelerator 1390 supports more thanone transport profile, network orchestrator 1380 chooses which transportprofile said hardware accelerator should be configured with. In at leastone embodiment, if hardware accelerator 1390 supports instantiation ofmore than one virtual hardware devices (also known as virtual devices orvirtual machines) from one physical hardware accelerator, differentvirtual devices may be configured with different transport profiles ifsupported.

In at least one embodiment, network orchestrator 1380, upon receivingacknowledgement of transport configurations, deploys an application 1348with a hardware accelerator configured with a transport profile (e.g., afile containing transport configuration parameters), compatible withapplication 1302. In at least one embodiment, application 1320 isagnostic as to what resources, including transport configurations, areavailable to a hardware accelerator 1390. In at least one embodiment,application calls transport abstraction APIs to send and/or receive datato and/or from application to hardware accelerator over an abstractedtransport layer, which is described further herein including inconjunction with at least FIG. 2 . In at least one embodiment,application 1320 calls buffer_alloc( ) API 1350. In at least oneembodiment, calling buffer_alloc( ) API 1350 causes operations to beperformed as follows: return pool id 1351 a (memory pool identificationinformation) and increment ref_count 1351 b, which are described furtherherein including in conjunction with at least FIG. 2 . In at least oneembodiment, application 1320 calls buffer_send( ) API 1352, which causesoperations to be performed as follows: send data 1353 a and sendacknowledgement (ACK) 1353 b from hardware accelerator 1390 toapplication 1320 that said data was sent. In at least one embodiment,application 1320 calls buffer_release( ) API 1358, which causesoperations to be performed as follows: decrement a reference counter1358 a and release a buffer back to a buffer pool 1358 b. One or moreaspects of one or more embodiments described in conjunction with FIG. 13can be combined with one or more aspects of one or more embodimentsdescribed in conjunction with FIGS. 1-12 and 14-15 .

FIG. 14 illustrates a call flow diagram 1400 for calls between a networkorchestrator, applications, and accelerator, according to at least oneembodiment. In at least one embodiment, diagram 1400 includes networkorchestrator 1480, hardware accelerator 1490 running virtual devices1498, and applications 1420 used in a disaggregated network includingvirtual devices. In at least one embodiment, diagram 1400 begins withnetwork orchestrator querying 1440 a hardware accelerator's 1490capabilities, including what transport profiles hardware accelerator1490 supports and how many virtual devices hardware accelerator 1490 caninstantiate. In at least one embodiment, hardware accelerator 1490includes device driver 1492 and libraries 1494. In at least oneembodiment, hardware accelerator 1490 returns 1442 its capabilities tonetwork orchestrator 1480, including supported transport profiles and anumber of instantiable virtual devices. In at least one embodiment,network orchestrator 1480 sets 1444 n number of virtual devices, whereinn<=N, with configurations for m number of transport profiles, whereinm<=M. In at least one embodiment, network orchestrator 1480 configures1446 each virtual device with transport profiles (e.g., TF1, TF2, . . ., TFn), wherein said transport profiles may include one or more types oftransport profiles. In at least one embodiment, if hardware accelerator1490 supports more than one transport profile, network orchestrator 1480chooses how to configure each virtual device with respect to theirtransport profiles, for example, network orchestrator 1480 may choose toconfigure each virtual device with specific transport profiles based ona subsequent application deployment.

In at least one embodiment, network orchestrator 1480, upon receivingacknowledgment 1448 of transport configurations for each virtual device,deploys 1448 a plurality of applications with transport-configuredvirtual devices, for example, application 1 1420 a is deployed withvirtual device 1 1498 a that is configured with transport profile 1(TF1). In at least one embodiment, applications 1420 include one or moretypes of applications, for example, applications include only L2+applications, or in another example, applications include a combinationof distributed unit (DU), centralized unit (CU), and RAN intelligentcontroller (MC) applications, each with different accelerationworkloads. In at least one embodiment, each application of applications1420 independently invokes transport abstraction APIs 1449 to sendand/or receive data to and/or from an application assigned to a virtualdevice over an abstracted transport layer. In at least one embodiment,transport abstraction APIs are mapped to various transport profiles on ahardware accelerator that runs virtual devices. One or more aspects ofone or more embodiments described in conjunction with FIG. 14 can becombined with one or more aspects of one or more embodiments describedin conjunction with FIGS. 1-13 and 15A-15B.

FIG. 15A illustrates a process 1500 for abstracted transport ofinformation between two 5G-NR computing resources, according to at leastone embodiment. In at least one embodiment, process 1500 begins withcalling an API from a 5G-NR computing resource during operation 1310. Inat least one embodiment, a 5G-NR computing resource in operation 1510uses one or more specific transport configurations. In at least oneembodiment, an API in operation 1510 includes a transport abstractionAPI described further herein at least in conjunction with FIGS. 1-14 and15B. In at least one embodiment, an API in operation 1510 includesbuffer_alloc( ), buffer_clone( ), buffer_send( ), buffer_recv( ), andbuffer_release( ). In at least one embodiment, a 5G-NR computingresource may include an L2+ application.

In at least one embodiment, after calling an API with operation 1510,process 1500 includes abstracting information from said 5G-NR computingresource during operation 1515. In at least one embodiment, abstractinginformation during operation 1515 includes a process of mapping anoperation from one transport configuration to another operation fromanother transport configuration. In at least one embodiment, abstractinginformation during operation 1515 includes identifying what operationrelated to a specific transport configuration should be performed basedon a transport abstraction API call made by an application, which isdiscussed further herein at least in conjunction with FIGS. 1-14 and15B.

In at least one embodiment, using abstracted information from operation1515, process 1500 continues by causing an operation on another 5G-NRcomputing resource to be performed during operation 1520. In at leastone embodiment, another 5G-NR computing resource in operation 1520 usesone or more specific transport configurations that differ from transportconfigurations used by a 5G-NR computing resource in operation 1510. Inat least one embodiment, aspects of operation 1520 are described furtherherein at least in conjunction with FIGS. 1-14 and 15B. One or moreaspects of one or more embodiments described in conjunction with FIG. 15can be combined with one or more aspects of one or more embodimentsdescribed in conjunction with FIGS. 1-14 and 15B.

FIG. 15B illustrates a table 1550 that associates transport abstractionAPIs with reference counts, according to at least one embodiment. In atleast one embodiment, table 1550 illustrates and example of one or moretransport abstraction APIs, such as those discussed herein at least inconjunction with FIG. 2 , can be embedded in a prior or posterior(following) API along with an additional input parameter, for example,instead of having a dedicated buffer_clone( ) API to inform bufferownership retention by an application, buffer_clone( ), its equivalent,or similar is embedded in a prior (e.g., buffer_alloc( )) and/orposterior (e.g., buffer_send( )) API with an additional input parameter(indication). In at least one embodiment, due to an API embedded in aprior or posterior API along with an additional indication, ref_countincrement and/or decrement operations at an implementation side can bedifferent (instead of always being +1 or −1). In at least oneembodiment, table 1550 explains ref_count changes via an example(Option 1) including an explicit buffer_clone( ) API call for bufferretention, an example (Option 2a) including an implicit indication ofbuffer retention in buffer_alloc( ), and an example (Option 2b)including implicit indication of buffer retention in buffer_send( ). Inat least one embodiment, Options 2a and 2b include buffer_retain( ) APIsembedded in corresponding APIs. One or more aspects of one or moreembodiments described in conjunction with FIG. 15B can be combined withone or more aspects of one or more embodiments described in conjunctionwith FIGS. 1-15A.

Data Center

FIG. 16 illustrates an example data center 1600, in which at least oneembodiment may be used. In at least one embodiment, data center 1600includes a data center infrastructure layer 1610, a framework layer1620, a software layer 1630 and an application layer 1640.

In at least one embodiment, as shown in FIG. 16 , data centerinfrastructure layer 1610 may include a resource orchestrator 1612,grouped computing resources 1614, and node computing resources (“nodeC.R.s”) 1616(1)-1616(N), where “N” represents any whole, positiveinteger. In at least one embodiment, node C.R.s 1616(1)-1616(N) mayinclude, but are not limited to, any number of central processing units(“CPUs”) or other processors (including accelerators, field programmablegate arrays (FPGAs), graphics processors, etc.), memory devices (e.g.,dynamic read-only memory), storage devices (e.g., solid state or diskdrives), network input/output (“NW I/O”) devices, network switches,virtual machines (“VMs”), power modules, and cooling modules, etc. In atleast one embodiment, one or more node C.R.s from among node C.R.s1616(1)-1616(N) may be a server having one or more of above-mentionedcomputing resources.

In at least one embodiment, grouped computing resources 1614 may includeseparate groupings of node C.R.s housed within one or more racks (notshown), or many racks housed in data centers at various geographicallocations (also not shown). In at least one embodiment, separategroupings of node C.R.s within grouped computing resources 1614 mayinclude grouped compute, network, memory, or storage resources that maybe configured or allocated to support one or more workloads. In at leastone embodiment, several node C.R.s including CPUs or processors maygrouped within one or more racks to provide compute resources to supportone or more workloads. In at least one embodiment, one or more racks mayalso include any number of power modules, cooling modules, and networkswitches, in any combination.

In at least one embodiment, resource orchestrator 1612 may configure orotherwise control one or more node C.R.s 1616(1)-1616(N) and/or groupedcomputing resources 1614. In at least one embodiment, resourceorchestrator 1612 may include a software design infrastructure (“SDI”)management entity for data center 1600. In at least one embodiment,resource orchestrator may include hardware, software, or somecombination thereof.

In at least one embodiment, as shown in FIG. 16 , framework layer 1620includes a job scheduler 1632, a configuration manager 1634, a resourcemanager 1636 and a distributed file system 1638. In at least oneembodiment, framework layer 1620 may include a framework to supportsoftware 1632 of software layer 1630 and/or one or more application(s)1642 of application layer 1640. In at least one embodiment, software1632 or application(s) 1642 may respectively include web-based servicesoftware or applications, such as those provided by Amazon Web Services,Google Cloud and Microsoft Azure. In at least one embodiment, frameworklayer 1620 may be, but is not limited to, a type of free and open-sourcesoftware web application framework such as Apache Spar™ (hereinafter“Spark”) that may utilize distributed file system 1638 for large-scaledata processing (e.g., “big data”). In at least one embodiment, jobscheduler 1632 may include a Spark driver to facilitate scheduling ofworkloads supported by various layers of data center 1600. In at leastone embodiment, configuration manager 1634 may be capable of configuringdifferent layers such as software layer 1630 and framework layer 1620including Spark and distributed file system 1638 for supportinglarge-scale data processing. In at least one embodiment, resourcemanager 1636 may be capable of managing clustered or grouped computingresources mapped to or allocated for support of distributed file system1638 and job scheduler 1632. In at least one embodiment, clustered orgrouped computing resources may include grouped computing resource 1614at data center infrastructure layer 1610. In at least one embodiment,resource manager 1636 may coordinate with resource orchestrator 1612 tomanage these mapped or allocated computing resources.

In at least one embodiment, software 1632 included in software layer1630 may include software used by at least portions of node C.R.s1616(1)-1616(N), grouped computing resources 1614, and/or distributedfile system 1638 of framework layer 1620. In at least one embodiment,one or more types of software may include, but are not limited to,Internet web page search software, e-mail virus scan software, databasesoftware, and streaming video content software.

In at least one embodiment, application(s) 1642 included in applicationlayer 1640 may include one or more types of applications used by atleast portions of node C.R.s 1616(1)-1616(N), grouped computingresources 1614, and/or distributed file system 1638 of framework layer1620. In at least one embodiment, one or more types of applications mayinclude, but are not limited to, any number of a genomics application, acognitive compute, and a machine learning application, includingtraining or inferencing software, machine learning framework software(e.g., PyTorch, TensorFlow, Caffe, etc.) or other machine learningapplications used in conjunction with one or more embodiments.

In at least one embodiment, any of configuration manager 1634, resourcemanager 1636, and resource orchestrator 1612 may implement any numberand type of self-modifying actions based on any amount and type of dataacquired in any technically feasible fashion. In at least oneembodiment, self-modifying actions may relieve a data center operator ofdata center 1600 from making possibly bad configuration decisions andpossibly avoiding underutilized and/or poor performing portions of adata center.

In at least one embodiment, data center 1600 may include tools,services, software, or other resources to train one or more machinelearning models or predict or infer information using one or moremachine learning models according to one or more embodiments describedherein. For example, in at least one embodiment, a machine learningmodel may be trained by calculating weight parameters according to aneural network architecture using software and computing resourcesdescribed above with respect to data center 1600. In at least oneembodiment, trained machine learning models corresponding to one or moreneural networks may be used to infer or predict information usingresources described above with respect to data center 1600 by usingweight parameters calculated through one or more training techniquesdescribed herein.

In at least one embodiment, data center 1600 may use CPUs,application-specific integrated circuits (ASICs), GPUs, FPGAs, or otherhardware to perform training and/or inferencing using above-describedresources. Moreover, one or more software and/or hardware resourcesdescribed above may be configured as a service to allow users to trainor performing inferencing of information, such as image recognition,speech recognition, or other artificial intelligence services. In atleast one embodiment, data center 1600 includes one or more CPUs, ASICs,GPUs, FPGAs, systems on chip (SoC), or other hardware, circuitry, orintegrated circuit components that include, e.g., an upscaler orupsampler to upscale an image, a sampler to sample an image (e.g., aspart of a DSP), a neural network circuit that is configured to performan upscaler to upscale an image (e.g., from a low resolution image to ahigh resolution image), or other hardware to modify or generate animage, frame, or video to adjust its resolution, size, or pixels; datacenter 1600 can use components described in this disclosure to performmethods, operations, or instructions that generate or modify an image.In at least one embodiment, at least one component shown or describedwith respect to FIG. 16 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-15B.

Autonomous vehicles may be described in terms of automation levels,defined by National Highway Traffic Safety Administration (“NHTSA”), adivision of US Department of Transportation, and Society of AutomotiveEngineers (“SAE”) “Taxonomy and Definitions for Terms Related to DrivingAutomation Systems for On-Road Motor Vehicles” (e.g., Standard No.J3016-201806, published on Jun. 15, 2018, Standard No. J3016-201609,published on Sep. 30, 2016, and previous and future versions of thisstandard). In one or more embodiments, vehicle 1700 may be capable offunctionality in accordance with one or more of level 1—level 5 ofautonomous driving levels. For example, in at least one embodiment,vehicle 1700 may be capable of conditional automation (Level 3), highautomation (Level 4), and/or full automation (Level 5), depending onembodiment.

In at least one embodiment, vehicle 1700 may include, withoutlimitation, components such as a chassis, a vehicle body, wheels (e.g.,2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle.In at least one embodiment, vehicle 1700 may include, withoutlimitation, a propulsion system 1750, such as an internal combustionengine, hybrid electric power plant, an all-electric engine, and/oranother propulsion system type. In at least one embodiment, propulsionsystem 1750 may be connected to a drive train of vehicle 1700, which mayinclude, without limitation, a transmission, to enable propulsion ofvehicle 1700. In at least one embodiment, propulsion system 1750 may becontrolled in response to receiving signals from athrottle/accelerator(s) 1752.

In at least one embodiment, a steering system 1754, which may include,without limitation, a steering wheel, is used to steer a vehicle 1700(e.g., along a desired path or route) when a propulsion system 1750 isoperating (e.g., when vehicle is in motion). In at least one embodiment,a steering system 1754 may receive signals from steering actuator(s)1756. In at least one embodiment, steering wheel may be optional forfull automation (Level 5) functionality. In at least one embodiment, abrake sensor system 1746 may be used to operate vehicle brakes inresponse to receiving signals from brake actuator(s) 1748 and/or brakesensors.

In at least one embodiment, controller(s) 1736, which may include,without limitation, one or more system on chips (“SoCs”) (not shown inFIG. 17A) and/or graphics processing unit(s) (“GPU(s)”), provide signals(e.g., representative of commands) to one or more components and/orsystems of vehicle 1700. For instance, in at least one embodiment,controller(s) 1736 may send signals to operate vehicle brakes via brakeactuators 1748, to operate steering system 1754 via steering actuator(s)1756, to operate propulsion system 1750 via throttle/accelerator(s)1752. In at least one embodiment, controller(s) 1736 may include one ormore onboard (e.g., integrated) computing devices (e.g., supercomputers)that process sensor signals, and output operation commands (e.g.,signals representing commands) to enable autonomous driving and/or toassist a human driver in driving vehicle 1700. In at least oneembodiment, controller(s) 1736 may include a first controller 1736 forautonomous driving functions, a second controller 1736 for functionalsafety functions, a third controller 1736 for artificial intelligencefunctionality (e.g., computer vision), a fourth controller 1736 forinfotainment functionality, a fifth controller 1736 for redundancy inemergency conditions, and/or other controllers. In at least oneembodiment, a single controller 1736 may handle two or more of abovefunctionalities, two or more controllers 1736 may handle a singlefunctionality, and/or any combination thereof.

In at least one embodiment, controller(s) 1736 provide signals forcontrolling one or more components and/or systems of vehicle 1700 inresponse to sensor data received from one or more sensors (e.g., sensorinputs). In at least one embodiment, sensor data may be received from,for example and without limitation, global navigation satellite systems(“GNSS”) sensor(s) 1758 (e.g., Global Positioning System sensor(s)),RADAR sensor(s) 1760, ultrasonic sensor(s) 1762, LIDAR sensor(s) 1764,inertial measurement unit (“IMU”) sensor(s) 1766 (e.g.,accelerometer(s), gyroscope(s), magnetic compass(es), magnetometer(s),etc.), microphone(s) 1796, stereo camera(s) 1768, wide-view camera(s)1770 (e.g., fisheye cameras), infrared camera(s) 1772, surroundcamera(s) 1774 (e.g., 360 degree cameras), long-range cameras (not shownin FIG. 17A), mid-range camera(s) (not shown in FIG. 17A), speedsensor(s) 1744 (e.g., for measuring speed of vehicle 1700), vibrationsensor(s) 1742, steering sensor(s) 1740, brake sensor(s) (e.g., as partof brake sensor system 1746), and/or other sensor types.

In at least one embodiment, one or more of controller(s) 1736 mayreceive inputs (e.g., represented by input data) from an instrumentcluster 1732 of vehicle 1700 and provide outputs (e.g., represented byoutput data, display data, etc.) via a human-machine interface (“HMI”)display 1734, an audible annunciator, a loudspeaker, and/or via othercomponents of vehicle 1700. In at least one embodiment, outputs mayinclude information such as vehicle velocity, speed, time, map data(e.g., a High Definition map (not shown in FIG. 17A), location data(e.g., vehicle's 1700 location, such as on a map), direction, locationof other vehicles (e.g., an occupancy grid), information about objectsand status of objects as perceived by controller(s) 1736, etc. Forexample, in at least one embodiment, HMI display 1734 may displayinformation about presence of one or more objects (e.g., a street sign,caution sign, traffic light changing, etc.), and/or information aboutdriving maneuvers vehicle has made, is making, or will make (e.g.,changing lanes now, taking exit 34B in two miles, etc.).

In at least one embodiment, vehicle 1700 further includes a networkinterface 1724 which may use wireless antenna(s) 1726 and/or modem(s) tocommunicate over one or more networks. For example, in at least oneembodiment, network interface 1724 may be capable of communication overLong-Term Evolution (“LTE”), Wideband Code Division Multiple Access(“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), GlobalSystem for Mobile communication (“GSM”), IMT-CDMA Multi-Carrier(“CDMA2000”), etc. In at least one embodiment, wireless antenna(s) 1726may also enable communication between objects in environment (e.g.,vehicles, mobile devices, etc.), using local area network(s), such asBluetooth, Bluetooth Low Energy (“LE”), Z-Wave, ZigBee, etc., and/or lowpower wide-area network(s) (“LPWANs”), such as LoRaWAN, SigFox, etc. Inat least one embodiment, vehicle 1700 further includes one or more CPUs,ASICs, GPUs, FPGAs, systems on chip (SoC), or other hardware, circuitry,or integrated circuit components that include, e.g., an upscaler orupsampler to upscale an image, a sampler to sample an image (e.g., aspart of a DSP), a neural network circuit that is configured to performan upscaler to upscale an image (e.g., from a low resolution image to ahigh resolution image), or other hardware to modify or generate animage, frame, or video to adjust its resolution, size, or pixels. In atleast one embodiment, at least one component shown or described withrespect to FIG. 17A is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-15B.

FIG. 17B illustrates an example of camera locations and fields of viewfor autonomous vehicle 1700 of FIG. 17A, according to at least oneembodiment. In at least one embodiment, cameras and respective fields ofview are one example embodiment and are not intended to be limiting. Forinstance, in at least one embodiment, additional and/or alternativecameras may be included and/or cameras may be located at differentlocations on vehicle 1700.

In at least one embodiment, camera types for cameras may include, butare not limited to, digital cameras that may be adapted for use withcomponents and/or systems of vehicle 1700. In at least one embodiment,camera(s) may operate at automotive safety integrity level (“ASIL”) Band/or at another ASIL. In at least one embodiment, camera types may becapable of any image capture rate, such as 60 frames per second (fps),1220 fps, 240 fps, etc., depending on embodiment. In at least oneembodiment, cameras may be capable of using rolling shutters, globalshutters, another type of shutter, or a combination thereof. In at leastone embodiment, color filter array may include a red clear clear clear(“RCCC”) color filter array, a red clear clear blue (“RCCB”) colorfilter array, a red blue green clear (“RBGC”) color filter array, aFoveon X3 color filter array, a Bayer sensors (“RGGB”) color filterarray, a monochrome sensor color filter array, and/or another types ofcolor filter arrays. In at least one embodiment, clear pixel cameras,such as cameras with an RCCC, an RCCB, and/or an RBGC color filterarray, may be used in an effort to increase light sensitivity.

In at least one embodiment, one or more of camera(s) may be used toperform advanced driver assistance systems (“ADAS”) functions (e.g., aspart of a redundant or fail-safe design). For example, in at least oneembodiment, a Multi-Function Mono Camera may be installed to providefunctions including lane departure warning, traffic sign assist andintelligent headlamp control. In at least one embodiment, one or more ofcamera(s) (e.g., all of cameras) may record and provide image data(e.g., video) simultaneously.

In at least one embodiment, one or more cameras may be mounted in amounting assembly, such as a custom designed (three-dimensional (“3D”)printed) assembly, in order to cut out stray light and reflections fromwithin a car (e.g., reflections from dashboard reflected in windshieldmirrors) which may interfere with a camera's image data captureabilities. With reference to wing-mirror mounting assemblies, in atleast one embodiment, wing-mirror assemblies may be custom 3D printed sothat camera mounting plate matches shape of wing-mirror. In at least oneembodiment, camera(s) may be integrated into wing-mirror. In at leastone embodiment, for side-view cameras, camera(s) may also be integratedwithin four pillars at each corner of car.

In at least one embodiment, cameras with a field of view that includeportions of environment in front of vehicle 1700 (e.g., front-facingcameras) may be used for surround view, to help identify forward facingpaths and obstacles, as well as aid in, with help of one or more ofcontrollers 1736 and/or control SoCs, providing information critical togenerating an occupancy grid and/or determining preferred vehicle paths.In at least one embodiment, front-facing cameras may be used to performmany of same ADAS functions as LIDAR, including, without limitation,emergency braking, pedestrian detection, and collision avoidance. In atleast one embodiment, front-facing cameras may also be used for ADASfunctions and systems including, without limitation, Lane DepartureWarnings (“LDW”), Autonomous Cruise Control (“ACC”), and/or otherfunctions such as traffic sign recognition.

In at least one embodiment, a variety of cameras may be used in afront-facing configuration, including, for example, a monocular cameraplatform that includes a CMOS (“complementary metal oxidesemiconductor”) color imager. In at least one embodiment, wide-viewcamera 1770 may be used to perceive objects coming into view fromperiphery (e.g., pedestrians, crossing traffic or bicycles). Althoughonly one wide-view camera 1770 is illustrated in FIG. 17B, in otherembodiments, there may be any number (including zero) of wide-viewcamera(s) 1770 on vehicle 1700. In at least one embodiment, any numberof long-range camera(s) 1798 (e.g., a long-view stereo camera pair) maybe used for depth-based object detection, especially for objects forwhich a neural network has not yet been trained. In at least oneembodiment, long-range camera(s) 1798 may also be used for objectdetection and classification, as well as basic object tracking.

In at least one embodiment, any number of stereo camera(s) 1768 may alsobe included in a front-facing configuration. In at least one embodiment,one or more of stereo camera(s) 1768 may include an integrated controlunit comprising a scalable processing unit, which may provide aprogrammable logic (“FPGA”) and a multi-core micro-processor with anintegrated Controller Area Network (“CAN”) or Ethernet interface on asingle chip. In at least one embodiment, such a unit may be used togenerate a 3D map of environment of vehicle 1700, including a distanceestimate for all points in image. In at least one embodiment, one ormore of stereo camera(s) 1768 may include, without limitation, compactstereo vision sensor(s) that may include, without limitation, two cameralenses (one each on left and right) and an image processing chip thatmay measure distance from vehicle 1700 to target object and usegenerated information (e.g., metadata) to activate autonomous emergencybraking and lane departure warning functions. In at least oneembodiment, other types of stereo camera(s) 1768 may be used in additionto, or alternatively from, those described herein.

In at least one embodiment, cameras with a field of view that includeportions of environment to side of vehicle 1700 (e.g., side-viewcameras) may be used for surround view, providing information used tocreate and update occupancy grid, as well as to generate side impactcollision warnings. For example, in at least one embodiment, surroundcamera(s) 1774 (e.g., four surround cameras 1774 as illustrated in FIG.17B) could be positioned on vehicle 1700. In at least one embodiment,surround camera(s) 1774 may include, without limitation, any number andcombination of wide-view camera(s) 1770, fisheye camera(s), 360 degreecamera(s), and/or like. For instance, in at least one embodiment, fourfisheye cameras may be positioned on front, rear, and sides of vehicle1700. In at least one embodiment, vehicle 1700 may use three surroundcamera(s) 1774 (e.g., left, right, and rear), and may leverage one ormore other camera(s) (e.g., a forward-facing camera) as a fourthsurround-view camera.

In at least one embodiment, cameras with a field of view that includeportions of environment to rear of vehicle 1700 (e.g., rear-viewcameras) may be used for park assistance, surround view, rear collisionwarnings, and creating and updating occupancy grid. In at least oneembodiment, a wide variety of cameras may be used including, but notlimited to, cameras that are also suitable as a front-facing camera(s)(e.g., long-range cameras 1798 and/or mid-range camera(s) 1776, stereocamera(s) 1768), infrared camera(s) 1772, etc.), as described herein. Inat least one embodiment, at least one component shown or described withrespect to FIG. 17B is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-15B.

FIG. 17C is a block diagram illustrating an example system architecturefor autonomous vehicle 1700 of FIG. 17A, according to at least oneembodiment. In at least one embodiment, each of components, features,and systems of vehicle 1700 in FIG. 17C are illustrated as beingconnected via a bus 1702. In at least one embodiment, bus 1702 mayinclude, without limitation, a CAN data interface (alternativelyreferred to herein as a “CAN bus”). In at least one embodiment, a CANmay be a network inside vehicle 1700 used to aid in control of variousfeatures and functionality of vehicle 1700, such as actuation of brakes,acceleration, braking, steering, windshield wipers, etc. In at least oneembodiment, bus 1702 may be configured to have dozens or even hundredsof nodes, each with its own unique identifier (e.g., a CAN ID). In atleast one embodiment, bus 1702 may be read to find steering wheel angle,ground speed, engine revolutions per minute (“RPMs”), button positions,and/or other vehicle status indicators. In at least one embodiment, bus1702 may be a CAN bus that is ASIL B compliant.

In at least one embodiment, in addition to, or alternatively from CAN,FlexRay and/or Ethernet may be used. In at least one embodiment, theremay be any number of busses 1702, which may include, without limitation,zero or more CAN busses, zero or more FlexRay busses, zero or moreEthernet busses, and/or zero or more other types of busses using adifferent protocol. In at least one embodiment, two or more busses 1702may be used to perform different functions, and/or may be used forredundancy. For example, a first bus 1702 may be used for collisionavoidance functionality and a second bus 1702 may be used for actuationcontrol. In at least one embodiment, each bus 1702 may communicate withany of components of vehicle 1700, and two or more busses 1702 maycommunicate with same components. In at least one embodiment, each ofany number of system(s) on chip(s) (“SoC(s)”) 1704, each ofcontroller(s) 1736, and/or each computer within vehicle may have accessto same input data (e.g., inputs from sensors of vehicle 1700), and maybe connected to a common bus, such CAN bus.

In at least one embodiment, vehicle 1700 may include one or morecontroller(s) 1736, such as those described herein with respect to FIG.17A. In at least one embodiment, controller(s) 1736 may be used for avariety of functions. In at least one embodiment, controller(s) 1736 maybe coupled to any of various other components and systems of vehicle1700, and may be used for control of vehicle 1700, artificialintelligence of vehicle 1700, infotainment for vehicle 1700, and/orlike.

In at least one embodiment, vehicle 1700 may include any number of SoCs1704. Each of SoCs 1704 may include, without limitation, centralprocessing units (“CPU(s)”) 1706, graphics processing units (“GPU(s)”)1708, processor(s) 1710, cache(s) 1712, accelerator(s) 1714, datastore(s) 1716, and/or other components and features not illustrated. Inat least one embodiment, SoC(s) 1704 may be used to control vehicle 1700in a variety of platforms and systems. For example, in at least oneembodiment, SoC(s) 1704 may be combined in a system (e.g., system ofvehicle 1700) with a High Definition (“HD”) map 1722 which may obtainmap refreshes and/or updates via network interface 1724 from one or moreservers (not shown in FIG. 17C).

In at least one embodiment, CPU(s) 1706 may include a CPU cluster or CPUcomplex (alternatively referred to herein as a “CCPLEX”). In at leastone embodiment, CPU(s) 1706 may include multiple cores and/or level two(“L2”) caches. For instance, in at least one embodiment, CPU(s) 1706 mayinclude eight cores in a coherent multi-processor configuration. In atleast one embodiment, CPU(s) 1706 may include four dual-core clusterswhere each cluster has a dedicated L2 cache (e.g., a 2 MB L2 cache). Inat least one embodiment, CPU(s) 1706 (e.g., CCPLEX) may be configured tosupport simultaneous cluster operation enabling any combination ofclusters of CPU(s) 1706 to be active at any given time.

In at least one embodiment, one or more of CPU(s) 1706 may implementpower management capabilities that include, without limitation, one ormore of following features: individual hardware blocks may beclock-gated automatically when idle to save dynamic power; each coreclock may be gated when core is not actively executing instructions dueto execution of Wait for Interrupt (“WFI”)/Wait for Event (“WFE”)instructions; each core may be independently power-gated; each corecluster may be independently clock-gated when all cores are clock-gatedor power-gated; and/or each core cluster may be independentlypower-gated when all cores are power-gated. In at least one embodiment,CPU(s) 1706 may further implement an enhanced algorithm for managingpower states, where allowed power states and expected wakeup times arespecified, and hardware/microcode determines best power state to enterfor core, cluster, and CCPLEX. In at least one embodiment, processingcores may support simplified power state entry sequences in softwarewith work offloaded to microcode.

In at least one embodiment, GPU(s) 1708 may include an integrated GPU(alternatively referred to herein as an “iGPU”). In at least oneembodiment, GPU(s) 1708 may be programmable and may be efficient forparallel workloads. In at least one embodiment, GPU(s) 1708, in at leastone embodiment, may use an enhanced tensor instruction set. In onembodiment, GPU(s) 1708 may include one or more streamingmicroprocessors, where each streaming microprocessor may include a levelone (“L1”) cache (e.g., an L1 cache with at least 96 KB storagecapacity), and two or more of streaming microprocessors may share an L2cache (e.g., an L2 cache with a 512 KB storage capacity). In at leastone embodiment, GPU(s) 1708 may include at least eight streamingmicroprocessors. In at least one embodiment, GPU(s) 1708 may use computeapplication programming interface(s) (API(s)). In at least oneembodiment, GPU(s) 1708 may use one or more parallel computing platformsand/or programming models (e.g., NVIDIA's CUDA).

In at least one embodiment, one or more of GPU(s) 1708 may bepower-optimized for best performance in automotive and embedded usecases. For example, in on embodiment, GPU(s) 1708 could be fabricated ona Fin field-effect transistor (“FinFET”). In at least one embodiment,each streaming microprocessor may incorporate a number ofmixed-precision processing cores partitioned into multiple blocks. Forexample, and without limitation, 64 PF32 cores and 32 PF64 cores couldbe partitioned into four processing blocks. In at least one embodiment,each processing block could be allocated 16 FP32 cores, 8 FP64 cores, 16INT32 cores, two mixed-precision NVIDIA TENSOR COREs for deep learningmatrix arithmetic, a level zero (“L0”) instruction cache, a warpscheduler, a dispatch unit, and/or a 64 KB register file. In at leastone embodiment, streaming microprocessors may include independentparallel integer and floating-point data paths to provide for efficientexecution of workloads with a mix of computation and addressingcalculations. In at least one embodiment, streaming microprocessors mayinclude independent thread scheduling capability to enable finer-grainsynchronization and cooperation between parallel threads. In at leastone embodiment, streaming microprocessors may include a combined L1 datacache and shared memory unit in order to improve performance whilesimplifying programming.

In at least one embodiment, one or more of GPU(s) 1708 may include ahigh bandwidth memory (“HBM) and/or a 16 GB HBM2 memory subsystem toprovide, in some examples, about 900 GB/second peak memory bandwidth. Inat least one embodiment, in addition to, or alternatively from, HBMmemory, a synchronous graphics random-access memory (“SGRAM”) may beused, such as a graphics double data rate type five synchronousrandom-access memory (“GDDR5”).

In at least one embodiment, GPU(s) 1708 may include unified memorytechnology. In at least one embodiment, address translation services(“ATS”) support may be used to allow GPU(s) 1708 to access CPU(s) 1706page tables directly. In at least one embodiment, embodiment, whenGPU(s) 1708 memory management unit (“MMU”) experiences a miss, anaddress translation request may be transmitted to CPU(s) 1706. Inresponse, CPU(s) 1706 may look in its page tables forvirtual-to-physical mapping for address and transmits translation backto GPU(s) 1708, in at least one embodiment. In at least one embodiment,unified memory technology may allow a single unified virtual addressspace for memory of both CPU(s) 1706 and GPU(s) 1708, therebysimplifying GPU(s) 1708 programming and porting of applications toGPU(s) 1708.

In at least one embodiment, GPU(s) 1708 may include any number of accesscounters that may keep track of frequency of access of GPU(s) 1708 tomemory of other processors. In at least one embodiment, accesscounter(s) may help ensure that memory pages are moved to physicalmemory of processor that is accessing pages most frequently, therebyimproving efficiency for memory ranges shared between processors.

In at least one embodiment, one or more of SoC(s) 1704 may include anynumber of cache(s) 1712, including those described herein. For example,in at least one embodiment, cache(s) 1712 could include a level three(“L3”) cache that is available to both CPU(s) 1706 and GPU(s) 1708(e.g., that is connected to both CPU(s) 1706 and GPU(s) 1708). In atleast one embodiment, cache(s) 1712 may include a write-back cache thatmay keep track of states of lines, such as by using a cache coherenceprotocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, L3cache may include 4 MB or more, depending on embodiment, althoughsmaller cache sizes may be used.

In at least one embodiment, one or more of SoC(s) 1704 may include oneor more accelerator(s) 1714 (e.g., hardware accelerators, softwareaccelerators, or a combination thereof). In at least one embodiment,SoC(s) 1704 may include a hardware acceleration cluster that may includeoptimized hardware accelerators and/or large on-chip memory. In at leastone embodiment, large on-chip memory (e.g., 4 MB of SRAM), may enablehardware acceleration cluster to accelerate neural networks and othercalculations. In at least one embodiment, hardware acceleration clustermay be used to complement GPU(s) 1708 and to off-load some of tasks ofGPU(s) 1708 (e.g., to free up more cycles of GPU(s) 1708 for performingother tasks). In at least one embodiment, accelerator(s) 1714 could beused for targeted workloads (e.g., perception, convolutional neuralnetworks (“CNNs”), recurrent neural networks (“RNNs”), etc.) that arestable enough to be amenable to acceleration. In at least oneembodiment, a CNN may include a region-based or regional convolutionalneural networks (“RCNNs”) and Fast RCNNs (e.g., as used for objectdetection) or other type of CNN.

In at least one embodiment, accelerator(s) 1714 (e.g., hardwareacceleration cluster) may include a deep learning accelerator(s) (“DLA).DLA(s) may include, without limitation, one or more Tensor processingunits (“TPUs) that may be configured to provide an additional tentrillion operations per second for deep learning applications andinferencing. In at least one embodiment, TPUs may be acceleratorsconfigured to, and optimized for, performing image processing functions(e.g., for CNNs, RCNNs, etc.). DLA(s) may further be optimized for aspecific set of neural network types and floating point operations, aswell as inferencing. In at least one embodiment, design of DLA(s) mayprovide more performance per millimeter than a typical general-purposeGPU, and typically vastly exceeds performance of a CPU. In at least oneembodiment, TPU(s) may perform several functions, including asingle-instance convolution function, supporting, for example, INT8,INT16, and FP16 data types for both features and weights, as well aspost-processor functions. In at least one embodiment, DLA(s) may quicklyand efficiently execute neural networks, especially CNNs, on processedor unprocessed data for any of a variety of functions, including, forexample and without limitation: a CNN for object identification anddetection using data from camera sensors; a CNN for distance estimationusing data from camera sensors; a CNN for emergency vehicle detectionand identification and detection using data from microphones 1796; a CNNfor facial recognition and vehicle owner identification using data fromcamera sensors; and/or a CNN for security and/or safety related events.

In at least one embodiment, DLA(s) may perform any function of GPU(s)1708, and by using an inference accelerator, for example, a designer maytarget either DLA(s) or GPU(s) 1708 for any function. For example, in atleast one embodiment, designer may focus processing of CNNs and floatingpoint operations on DLA(s) and leave other functions to GPU(s) 1708and/or other accelerator(s) 1714.

In at least one embodiment, accelerator(s) 1714 (e.g., hardwareacceleration cluster) may include a programmable vision accelerator(s)(“PVA”), which may alternatively be referred to herein as a computervision accelerator. In at least one embodiment, PVA(s) may be designedand configured to accelerate computer vision algorithms for advanceddriver assistance system (“ADAS”) 1738, autonomous driving, augmentedreality (“AR”) applications, and/or virtual reality (“VR”) applications.PVA(s) may provide a balance between performance and flexibility. Forexample, in at least one embodiment, each PVA(s) may include, forexample and without limitation, any number of reduced instruction setcomputer (“RISC”) cores, direct memory access (“DMA”), and/or any numberof vector processors.

In at least one embodiment, RISC cores may interact with image sensors(e.g., image sensors of any of cameras described herein), image signalprocessor(s), and/or like. In at least one embodiment, each of RISCcores may include any amount of memory. In at least one embodiment, RISCcores may use any of a number of protocols, depending on embodiment. Inat least one embodiment, RISC cores may execute a real-time operatingsystem (“RTOS”). In at least one embodiment, RISC cores may beimplemented using one or more integrated circuit devices, applicationspecific integrated circuits (“ASICs”), and/or memory devices. Forexample, in at least one embodiment, RISC cores could include aninstruction cache and/or a tightly coupled RAM.

In at least one embodiment, DMA may enable components of PVA(s) toaccess system memory independently of CPU(s) 1706. In at least oneembodiment, DMA may support any number of features used to provideoptimization to PVA including, but not limited to, supportingmulti-dimensional addressing and/or circular addressing. In at least oneembodiment, DMA may support up to six or more dimensions of addressing,which may include, without limitation, block width, block height, blockdepth, horizontal block stepping, vertical block stepping, and/or depthstepping.

In at least one embodiment, vector processors may be programmableprocessors that may be designed to efficiently and flexibly executeprogramming for computer vision algorithms and provide signal processingcapabilities. In at least one embodiment, PVA may include a PVA core andtwo vector processing subsystem partitions. In at least one embodiment,PVA core may include a processor subsystem, DMA engine(s) (e.g., two DMAengines), and/or other peripherals. In at least one embodiment, vectorprocessing subsystem may operate as a primary processing engine of PVAand may include a vector processing unit (“VPU”), an instruction cache,and/or vector memory (e.g., “VMEM”). In at least one embodiment, VPUcore may include a digital signal processor such as, for example, asingle instruction, multiple data (“SIMD”), very long instruction word(“VLIW”) digital signal processor. In at least one embodiment, acombination of SIMD and VLIW may enhance throughput and speed.

In at least one embodiment, each of vector processors may include aninstruction cache and may be coupled to dedicated memory. As a result,in at least one embodiment, each of vector processors may be configuredto execute independently of other vector processors. In at least oneembodiment, vector processors that are included in a particular PVA maybe configured to employ data parallelism. For instance, in at least oneembodiment, plurality of vector processors included in a single PVA mayexecute same computer vision algorithm, but on different regions of animage. In at least one embodiment, vector processors included in aparticular PVA may simultaneously execute different computer visionalgorithms, on same image, or even execute different algorithms onsequential images or portions of an image. In at least one embodiment,among other things, any number of PVAs may be included in hardwareacceleration cluster and any number of vector processors may be includedin each of PVAs. In at least one embodiment, PVA(s) may includeadditional error correcting code (“ECC”) memory, to enhance overallsystem safety.

In at least one embodiment, accelerator(s) 1714 (e.g., hardwareacceleration cluster) may include a computer vision network on-chip andstatic random-access memory (“SRAM”), for providing a high-bandwidth,low latency SRAM for accelerator(s) 1714. In at least one embodiment,on-chip memory may include at least 4 MB SRAM, consisting of, forexample and without limitation, eight field-configurable memory blocks,that may be accessible by both PVA and DLA. In at least one embodiment,each pair of memory blocks may include an advanced peripheral bus(“APB”) interface, configuration circuitry, a controller, and amultiplexer. In at least one embodiment, any type of memory may be used.In at least one embodiment, PVA and DLA may access memory via a backbonethat provides PVA and DLA with high-speed access to memory. In at leastone embodiment, backbone may include a computer vision network on-chipthat interconnects PVA and DLA to memory (e.g., using APB).

In at least one embodiment, computer vision network on-chip may includean interface that determines, before transmission of any controlsignal/address/data, that both PVA and DLA provide ready and validsignals. In at least one embodiment, an interface may provide forseparate phases and separate channels for transmitting controlsignals/addresses/data, as well as burst-type communications forcontinuous data transfer. In at least one embodiment, an interface maycomply with International Organization for Standardization (“ISO”) 26262or International Electrotechnical Commission (“IEC”) 61508 standards,although other standards and protocols may be used.

In at least one embodiment, one or more of SoC(s) 1704 may include areal-time ray-tracing hardware accelerator. In at least one embodiment,real-time ray-tracing hardware accelerator may be used to quickly andefficiently determine positions and extents of objects (e.g., within aworld model), to generate real-time visualization simulations, for RADARsignal interpretation, for sound propagation synthesis and/or analysis,for simulation of SONAR systems, for general wave propagationsimulation, for comparison to LIDAR data for purposes of localizationand/or other functions, and/or for other uses.

In at least one embodiment, accelerator(s) 1714 (e.g., hardwareaccelerator cluster) have a wide array of uses for autonomous driving.In at least one embodiment, PVA may be a programmable vision acceleratorthat may be used for key processing stages in ADAS and autonomousvehicles. In at least one embodiment, PVA's capabilities are a goodmatch for algorithmic domains needing predictable processing, at lowpower and low latency. In other words, PVA performs well on semi-denseor dense regular computation, even on small data sets, which needpredictable run-times with low latency and low power. In at least oneembodiment, autonomous vehicles, such as vehicle 1700, PVAs are designedto run classic computer vision algorithms, as they are efficient atobject detection and operating on integer math.

For example, according to at least one embodiment of technology, PVA isused to perform computer stereo vision. In at least one embodiment,semi-global matching-based algorithm may be used in some examples,although this is not intended to be limiting. In at least oneembodiment, applications for Level 3-5 autonomous driving use motionestimation/stereo matching on-the-fly (e.g., structure from motion,pedestrian recognition, lane detection, etc.). In at least oneembodiment, PVA may perform computer stereo vision function on inputsfrom two monocular cameras.

In at least one embodiment, PVA may be used to perform dense opticalflow. For example, in at least one embodiment, PVA could process rawRADAR data (e.g., using a 4D Fast Fourier Transform) to provideprocessed RADAR data. In at least one embodiment, PVA is used fortime-of-flight depth processing, by processing raw time of flight datato provide processed time of flight data, for example.

In at least one embodiment, DLA may be used to run any type of networkto enhance control and driving safety, including for example and withoutlimitation, a neural network that outputs a measure of confidence foreach object detection. In at least one embodiment, confidence may berepresented or interpreted as a probability, or as providing a relative“weight” of each detection compared to other detections. In at least oneembodiment, confidence enables a system to make further decisionsregarding which detections should be considered as true positivedetections rather than false positive detections. In at least oneembodiment, a system may set a threshold value for confidence andconsider only detections exceeding threshold value as true positivedetections. In an embodiment in which an automatic emergency braking(“AEB”) system is used, false positive detections would cause vehicle toautomatically perform emergency braking, which is obviously undesirable.In at least one embodiment, highly confident detections may beconsidered as triggers for AEB. In at least one embodiment, DLA may runa neural network for regressing confidence value. In at least oneembodiment, neural network may take as its input at least some subset ofparameters, such as bounding box dimensions, ground plane estimateobtained (e.g., from another subsystem), output from IMU sensor(s) 1766that correlates with vehicle 1700 orientation, distance, 3D locationestimates of object obtained from neural network and/or other sensors(e.g., LIDAR sensor(s) 1764 or RADAR sensor(s) 1760), among others.

In at least one embodiment, one or more of SoC(s) 1704 may include datastore(s) 1716 (e.g., memory). In at least one embodiment, data store(s)1716 may be on-chip memory of SoC(s) 1704, which may store neuralnetworks to be executed on GPU(s) 1708 and/or DLA. In at least oneembodiment, data store(s) 1716 may be large enough in capacity to storemultiple instances of neural networks for redundancy and safety. In atleast one embodiment, data store(s) 1712 may comprise L2 or L3 cache(s).

In at least one embodiment, one or more of SoC(s) 1704 may include anynumber of processor(s) 1710 (e.g., embedded processors). In at least oneembodiment, processor(s) 1710 may include a boot and power managementprocessor that may be a dedicated processor and subsystem to handle bootpower and management functions and related security enforcement. In atleast one embodiment, boot and power management processor may be a partof SoC(s) 1704 boot sequence and may provide runtime power managementservices. In at least one embodiment, boot power and managementprocessor may provide clock and voltage programming, assistance insystem low power state transitions, management of SoC(s) 1704 thermalsand temperature sensors, and/or management of SoC(s) 1704 power states.In at least one embodiment, each temperature sensor may be implementedas a ring-oscillator whose output frequency is proportional totemperature, and SoC(s) 1704 may use ring-oscillators to detecttemperatures of CPU(s) 1706, GPU(s) 1708, and/or accelerator(s) 1714. Inat least one embodiment, if temperatures are determined to exceed athreshold, then boot and power management processor may enter atemperature fault routine and put SoC(s) 1704 into a lower power stateand/or put vehicle 1700 into a chauffeur to safe stop mode (e.g., bringvehicle 1700 to a safe stop).

In at least one embodiment, processor(s) 1710 may further include a setof embedded processors that may serve as an audio processing engine. Inat least one embodiment, audio processing engine may be an audiosubsystem that enables full hardware support for multi-channel audioover multiple interfaces, and a broad and flexible range of audio I/Ointerfaces. In at least one embodiment, audio processing engine is adedicated processor core with a digital signal processor with dedicatedRAM.

In at least one embodiment, processor(s) 1710 may further include analways on processor engine that may provide necessary hardware featuresto support low power sensor management and wake use cases. In at leastone embodiment, always on processor engine may include, withoutlimitation, a processor core, a tightly coupled RAM, supportingperipherals (e.g., timers and interrupt controllers), various I/Ocontroller peripherals, and routing logic.

In at least one embodiment, processor(s) 1710 may further include asafety cluster engine that includes, without limitation, a dedicatedprocessor subsystem to handle safety management for automotiveapplications. In at least one embodiment, safety cluster engine mayinclude, without limitation, two or more processor cores, a tightlycoupled RAM, support peripherals (e.g., timers, an interrupt controller,etc.), and/or routing logic. In a safety mode, two or more cores mayoperate, in at least one embodiment, in a lockstep mode and function asa single core with comparison logic to detect any differences betweentheir operations. In at least one embodiment, processor(s) 1710 mayfurther include a real-time camera engine that may include, withoutlimitation, a dedicated processor subsystem for handling real-timecamera management. In at least one embodiment, processor(s) 1710 mayfurther include a high-dynamic range signal processor that may include,without limitation, an image signal processor that is a hardware enginethat is part of camera processing pipeline.

In at least one embodiment, processor(s) 1710 may include a video imagecompositor that may be a processing block (e.g., implemented on amicroprocessor) that implements video post-processing functions neededby a video playback application to produce final image for playerwindow. In at least one embodiment, video image compositor may performlens distortion correction on wide-view camera(s) 1770, surroundcamera(s) 1774, and/or on in-cabin monitoring camera sensor(s). In atleast one embodiment, in-cabin monitoring camera sensor(s) arepreferably monitored by a neural network running on another instance ofSoC 1704, configured to identify in cabin events and respondaccordingly. In at least one embodiment, an in-cabin system may perform,without limitation, lip reading to activate cellular service and place aphone call, dictate emails, change vehicle's destination, activate orchange vehicle's infotainment system and settings, or providevoice-activated web surfing. In at least one embodiment, certainfunctions are available to driver when vehicle is operating in anautonomous mode and are disabled otherwise.

In at least one embodiment, video image compositor may include enhancedtemporal noise reduction for both spatial and temporal noise reduction.For example, in at least one embodiment, where motion occurs in a video,noise reduction weights spatial information appropriately, decreasingweight of information provided by adjacent frames. In at least oneembodiment, where an image or portion of an image does not includemotion, temporal noise reduction performed by video image compositor mayuse information from previous image to reduce noise in current image.

In at least one embodiment, video image compositor may also beconfigured to perform stereo rectification on input stereo lens frames.In at least one embodiment, video image compositor may further be usedfor user interface composition when operating system desktop is in use,and GPU(s) 1708 are not required to continuously render new surfaces. Inat least one embodiment, when GPU(s) 1708 are powered on and activedoing 3D rendering, video image compositor may be used to offload GPU(s)1708 to improve performance and responsiveness.

In at least one embodiment, one or more of SoC(s) 1704 may furtherinclude a mobile industry processor interface (“MIPI”) camera serialinterface for receiving video and input from cameras, a high-speedinterface, and/or a video input block that may be used for camera andrelated pixel input functions. In at least one embodiment, one or moreof SoC(s) 1704 may further include an input/output controller(s) thatmay be controlled by software and may be used for receiving I/O signalsthat are uncommitted to a specific role.

In at least one embodiment, one or more of SoC(s) 1704 may furtherinclude a broad range of peripheral interfaces to enable communicationwith peripherals, audio encoders/decoders (“codecs”), power management,and/or other devices. SoC(s) 1704 may be used to process data fromcameras (e.g., connected over Gigabit Multimedia Serial Link andEthernet), sensors (e.g., LIDAR sensor(s) 1764, RADAR sensor(s) 1760,etc. that may be connected over Ethernet), data from bus 1702 (e.g.,speed of vehicle 1700, steering wheel position, etc.), data from GNSSsensor(s) 1758 (e.g., connected over Ethernet or CAN bus), etc. In atleast one embodiment, one or more of SoC(s) 1704 may further includededicated high-performance mass storage controllers that may includetheir own DMA engines, and that may be used to free CPU(s) 1706 fromroutine data management tasks.

In at least one embodiment, SoC(s) 1704 may be an end-to-end platformwith a flexible architecture that spans automation levels 3-5, therebyproviding a comprehensive functional safety architecture that leveragesand makes efficient use of computer vision and ADAS techniques fordiversity and redundancy, provides a platform for a flexible, reliabledriving software stack, along with deep learning tools. In at least oneembodiment, SoC(s) 1704 may be faster, more reliable, and even moreenergy-efficient and space-efficient than conventional systems. Forexample, in at least one embodiment, accelerator(s) 1714, when combinedwith CPU(s) 1706, GPU(s) 1708, and data store(s) 1716, may provide for afast, efficient platform for level 3-5 autonomous vehicles.

In at least one embodiment, computer vision algorithms may be executedon CPUs, which may be configured using high-level programming language,such as C programming language, to execute a wide variety of processingalgorithms across a wide variety of visual data. However, in at leastone embodiment, CPUs are oftentimes unable to meet performancerequirements of many computer vision applications, such as those relatedto execution time and power consumption, for example. In at least oneembodiment, many CPUs are unable to execute complex object detectionalgorithms in real-time, which is used in in-vehicle ADAS applicationsand in practical Level 3-5 autonomous vehicles.

Embodiments described herein allow for multiple neural networks to beperformed simultaneously and/or sequentially, and for results to becombined together to enable Level 3-5 autonomous driving functionality.For example, in at least one embodiment, a CNN executing on DLA ordiscrete GPU (e.g., GPU(s) 1720) may include text and word recognition,allowing supercomputer to read and understand traffic signs, includingsigns for which neural network has not been specifically trained. In atleast one embodiment, DLA may further include a neural network that isable to identify, interpret, and provide semantic understanding of sign,and to pass that semantic understanding to path planning modules runningon CPU Complex.

In at least one embodiment, multiple neural networks may be runsimultaneously, as for Level 3, 4, or 5 driving. For example, in atleast one embodiment, a warning sign consisting of “Caution: flashinglights indicate icy conditions,” along with an electric light, may beindependently or collectively interpreted by several neural networks. Inat least one embodiment, sign itself may be identified as a traffic signby a first deployed neural network (e.g., a neural network that has beentrained), text “flashing lights indicate icy conditions” may beinterpreted by a second deployed neural network, which informs vehicle'spath planning software (preferably executing on CPU Complex) that whenflashing lights are detected, icy conditions exist. In at least oneembodiment, flashing light may be identified by operating a thirddeployed neural network over multiple frames, informing vehicle'spath-planning software of presence (or absence) of flashing lights. Inat least one embodiment, all three neural networks may runsimultaneously, such as within DLA and/or on GPU(s) 1708.

In at least one embodiment, a CNN for facial recognition and vehicleowner identification may use data from camera sensors to identifypresence of an authorized driver and/or owner of vehicle 1700. In atleast one embodiment, an always on sensor processing engine may be usedto unlock vehicle when owner approaches driver door and turn on lights,and, in security mode, to disable vehicle when owner leaves vehicle. Inthis way, SoC(s) 1704 provide for security against theft and/orcarjacking.

In at least one embodiment, a CNN for emergency vehicle detection andidentification may use data from microphones 1796 to detect and identifyemergency vehicle sirens. In at least one embodiment, SoC(s) 1704 useCNN for classifying environmental and urban sounds, as well asclassifying visual data. In at least one embodiment, CNN running on DLAis trained to identify relative closing speed of emergency vehicle(e.g., by using Doppler effect). In at least one embodiment, CNN mayalso be trained to identify emergency vehicles specific to local area inwhich vehicle is operating, as identified by GNSS sensor(s) 1758. In atleast one embodiment, when operating in Europe, CNN will seek to detectEuropean sirens, and when in United States CNN will seek to identifyonly North American sirens. In at least one embodiment, once anemergency vehicle is detected, a control program may be used to executean emergency vehicle safety routine, slowing vehicle, pulling over toside of road, parking vehicle, and/or idling vehicle, with assistance ofultrasonic sensor(s) 1762, until emergency vehicle(s) passes.

In at least one embodiment, vehicle 1700 may include CPU(s) 1718 (e.g.,discrete CPU(s), or dCPU(s)), that may be coupled to SoC(s) 1704 via ahigh-speed interconnect (e.g., PCIe). In at least one embodiment, CPU(s)1718 may include an X86 processor, for example. CPU(s) 1718 may be usedto perform any of a variety of functions, including arbitratingpotentially inconsistent results between ADAS sensors and SoC(s) 1704,and/or monitoring status and health of controller(s) 1736 and/or aninfotainment system on a chip (“infotainment SoC”) 1730, for example.

In at least one embodiment, vehicle 1700 may include GPU(s) 1720 (e.g.,discrete GPU(s), or dGPU(s)), that may be coupled to SoC(s) 1704 via ahigh-speed interconnect (e.g., NVIDIA's NVLINK). In at least oneembodiment, GPU(s) 1720 may provide additional artificial intelligencefunctionality, such as by executing redundant and/or different neuralnetworks and may be used to train and/or update neural networks based atleast in part on input (e.g., sensor data) from sensors of vehicle 1700.

In at least one embodiment, vehicle 1700 may further include networkinterface 1724 which may include, without limitation, wirelessantenna(s) 1726 (e.g., one or more wireless antennas 1726 for differentcommunication protocols, such as a cellular antenna, a Bluetoothantenna, etc.). In at least one embodiment, network interface 1724 maybe used to enable wireless connectivity over Internet with cloud (e.g.,with server(s) and/or other network devices), with other vehicles,and/or with computing devices (e.g., client devices of passengers). Inat least one embodiment, to communicate with other vehicles, a directlink may be established between vehicle 170 and other vehicle and/or anindirect link may be established (e.g., across networks and overInternet). In at least one embodiment, direct links may be providedusing a vehicle-to-vehicle communication link. In at least oneembodiment, vehicle-to-vehicle communication link may provide vehicle1700 information about vehicles in proximity to vehicle 1700 (e.g.,vehicles in front of, on side of, and/or behind vehicle 1700). In atleast one embodiment, aforementioned functionality may be part of acooperative adaptive cruise control functionality of vehicle 1700.

In at least one embodiment, network interface 1724 may include an SoCthat provides modulation and demodulation functionality and enablescontroller(s) 1736 to communicate over wireless networks. In at leastone embodiment, network interface 1724 may include a radio frequencyfront-end for up-conversion from baseband to radio frequency, and downconversion from radio frequency to baseband. In at least one embodiment,frequency conversions may be performed in any technically feasiblefashion. For example, frequency conversions could be performed throughwell-known processes, and/or using super-heterodyne processes. In atleast one embodiment, radio frequency front end functionality may beprovided by a separate chip. In at least one embodiment, networkinterface may include wireless functionality for communicating over LTE,WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave,ZigBee, LoRaWAN, and/or other wireless protocols.

In at least one embodiment, vehicle 1700 may further include datastore(s) 1728 which may include, without limitation, off-chip (e.g., offSoC(s) 1704) storage. In at least one embodiment, data store(s) 1728 mayinclude, without limitation, one or more storage elements including RAM,SRAM, dynamic random-access memory (“DRAM”), video random-access memory(“VRAM”), Flash, hard disks, and/or other components and/or devices thatmay store at least one bit of data.

In at least one embodiment, vehicle 1700 may further include GNSSsensor(s) 1758 (e.g., GPS and/or assisted GPS sensors), to assist inmapping, perception, occupancy grid generation, and/or path planningfunctions. In at least one embodiment, any number of GNSS sensor(s) 1758may be used, including, for example and without limitation, a GPS usinga USB connector with an Ethernet to Serial (e.g., RS-232) bridge.

In at least one embodiment, vehicle 1700 may further include RADARsensor(s) 1760. RADAR sensor(s) 1760 may be used by vehicle 1700 forlong-range vehicle detection, even in darkness and/or severe weatherconditions. In at least one embodiment, RADAR functional safety levelsmay be ASIL B. RADAR sensor(s) 1760 may use CAN and/or bus 1702 (e.g.,to transmit data generated by RADAR sensor(s) 1760) for control and toaccess object tracking data, with access to Ethernet to access raw datain some examples. In at least one embodiment, wide variety of RADARsensor types may be used. For example, and without limitation, RADARsensor(s) 1760 may be suitable for front, rear, and side RADAR use. Inat least one embodiment, one or more of RADAR sensors(s) 1760 are PulseDoppler RADAR sensor(s).

In at least one embodiment, RADAR sensor(s) 1760 may include differentconfigurations, such as long-range with narrow field of view,short-range with wide field of view, short-range side coverage, etc. Inat least one embodiment, long-range RADAR may be used for adaptivecruise control functionality. In at least one embodiment, long-rangeRADAR systems may provide a broad field of view realized by two or moreindependent scans, such as within a 250 m range. In at least oneembodiment, RADAR sensor(s) 1760 may help in distinguishing betweenstatic and moving objects, and may be used by ADAS system 1738 foremergency brake assist and forward collision warning. In at least oneembodiment, sensors 1760(s) included in a long-range RADAR system mayinclude, without limitation, monostatic multimodal RADAR with multiple(e.g., six or more) fixed RADAR antennae and a high-speed CAN andFlexRay interface. In at least one embodiment, with six antennae,central four antennae may create a focused beam pattern, designed torecord vehicle's 1700 surroundings at higher speeds with minimalinterference from traffic in adjacent lanes. In at least one embodiment,other two antennae may expand field of view, making it possible toquickly detect vehicles entering or leaving vehicle's 1700 lane.

In at least one embodiment, mid-range RADAR systems may include, as anexample, a range of up to 160 m (front) or 80 m (rear), and a field ofview of up to 42 degrees (front) or 150 degrees (rear). In at least oneembodiment, short-range RADAR systems may include, without limitation,any number of RADAR sensor(s) 1760 designed to be installed at both endsof rear bumper. When installed at both ends of rear bumper, in at leastone embodiment, a RADAR sensor system may create two beams thatconstantly monitor blind spot in rear and next to vehicle. In at leastone embodiment, short-range RADAR systems may be used in ADAS system1738 for blind spot detection and/or lane change assist.

In at least one embodiment, vehicle 1700 may further include ultrasonicsensor(s) 1762. In at least one embodiment, ultrasonic sensor(s) 1762,which may be positioned at front, back, and/or sides of vehicle 1700,may be used for park assist and/or to create and update an occupancygrid. In at least one embodiment, a wide variety of ultrasonic sensor(s)1762 may be used, and different ultrasonic sensor(s) 1762 may be usedfor different ranges of detection (e.g., 2.5 m, 4 m). In at least oneembodiment, ultrasonic sensor(s) 1762 may operate at functional safetylevels of ASIL B.

In at least one embodiment, vehicle 1700 may include LIDAR sensor(s)1764. LIDAR sensor(s) 1764 may be used for object and pedestriandetection, emergency braking, collision avoidance, and/or otherfunctions. In at least one embodiment, LIDAR sensor(s) 1764 may befunctional safety level ASIL B. In at least one embodiment, vehicle 1700may include multiple LIDAR sensors 1764 (e.g., two, four, six, etc.)that may use Ethernet (e.g., to provide data to a Gigabit Ethernetswitch).

In at least one embodiment, LIDAR sensor(s) 1764 may be capable ofproviding a list of objects and their distances for a 360-degree fieldof view. In at least one embodiment, commercially available LIDARsensor(s) 1764 may have an advertised range of approximately 100 m, withan accuracy of 2 cm-3 cm, and with support for a 100 Mbps Ethernetconnection, for example. In at least one embodiment, one or morenon-protruding LIDAR sensors 1764 may be used. In such an embodiment,LIDAR sensor(s) 1764 may be implemented as a small device that may beembedded into front, rear, sides, and/or corners of vehicle 1700. In atleast one embodiment, LIDAR sensor(s) 1764, in such an embodiment, mayprovide up to a 120-degree horizontal and 35-degree verticalfield-of-view, with a 200 m range even for low-reflectivity objects. Inat least one embodiment, front-mounted LIDAR sensor(s) 1764 may beconfigured for a horizontal field of view between 45 degrees and 135degrees.

In at least one embodiment, LIDAR technologies, such as 3D flash LIDAR,may also be used. 3D Flash LIDAR uses a flash of a laser as atransmission source, to illuminate surroundings of vehicle 1700 up toapproximately 200 m. In at least one embodiment, a flash LIDAR unitincludes, without limitation, a receptor, which records laser pulsetransit time and reflected light on each pixel, which in turncorresponds to range from vehicle 1700 to objects. In at least oneembodiment, flash LIDAR may allow for highly accurate anddistortion-free images of surroundings to be generated with every laserflash. In at least one embodiment, four flash LIDAR sensors may bedeployed, one at each side of vehicle 1700. In at least one embodiment,3D flash LIDAR systems include, without limitation, a solid-state 3Dstaring array LIDAR camera with no moving parts other than a fan (e.g.,a non-scanning LIDAR device). In at least one embodiment, flash LIDARdevice may use a 5 nanosecond class I (eye-safe) laser pulse per frameand may capture reflected laser light in form of 3D range point cloudsand co-registered intensity data.

In at least one embodiment, vehicle may further include IMU sensor(s)1766. In at least one embodiment, IMU sensor(s) 1766 may be located at acenter of rear axle of vehicle 1700, in at least one embodiment. In atleast one embodiment, IMU sensor(s) 1766 may include, for example andwithout limitation, accelerometer(s), magnetometer(s), gyroscope(s),magnetic compass(es), and/or other sensor types. In at least oneembodiment, such as in six-axis applications, IMU sensor(s) 1766 mayinclude, without limitation, accelerometers and gyroscopes. In at leastone embodiment, such as in nine-axis applications, IMU sensor(s) 1766may include, without limitation, accelerometers, gyroscopes, andmagnetometers.

In at least one embodiment, IMU sensor(s) 1766 may be implemented as aminiature, high performance GPS-Aided Inertial Navigation System(“GPS/INS”) that combines micro-electro-mechanical systems (“MEMS”)inertial sensors, a high-sensitivity GPS receiver, and advanced Kalmanfiltering algorithms to provide estimates of position, velocity, andattitude. In at least one embodiment, IMU sensor(s) 1766 may enablevehicle 1700 to estimate heading without requiring input from a magneticsensor by directly observing and correlating changes in velocity fromGPS to IMU sensor(s) 1766. In at least one embodiment, IMU sensor(s)1766 and GNSS sensor(s) 1758 may be combined in a single integratedunit.

In at least one embodiment, vehicle 1700 may include microphone(s) 1796placed in and/or around vehicle 1700. In at least one embodiment,microphone(s) 1796 may be used for emergency vehicle detection andidentification, among other things.

In at least one embodiment, vehicle 1700 may further include any numberof camera types, including stereo camera(s) 1768, wide-view camera(s)1770, infrared camera(s) 1772, surround camera(s) 1774, long-rangecamera(s) 1798, mid-range camera(s) 1776, and/or other camera types. Inat least one embodiment, cameras may be used to capture image dataaround an entire periphery of vehicle 1700. In at least one embodiment,types of cameras used depends vehicle 1700. In at least one embodiment,any combination of camera types may be used to provide necessarycoverage around vehicle 1700. In at least one embodiment, number ofcameras may differ depending on embodiment. For example, in at least oneembodiment, vehicle 1700 could include six cameras, seven cameras, tencameras, twelve cameras, or another number of cameras. In at least oneembodiment, cameras may support, as an example and without limitation,Gigabit Multimedia Serial Link (“GMSL”) and/or Gigabit Ethernet. In atleast one embodiment, each of camera(s) is described with more detailpreviously herein with respect to FIG. 17A and FIG. 17B.

In at least one embodiment, vehicle 1700 may further include vibrationsensor(s) 1742. In at least one embodiment, vibration sensor(s) 1742 maymeasure vibrations of components of vehicle 1700, such as axle(s). Forexample, in at least one embodiment, changes in vibrations may indicatea change in road surfaces. In at least one embodiment, when two or morevibration sensors 1742 are used, differences between vibrations may beused to determine friction or slippage of road surface (e.g., whendifference in vibration is between a power-driven axle and a freelyrotating axle).

In at least one embodiment, vehicle 1700 may include ADAS system 1738.ADAS system 1738 may include, without limitation, an SoC, in someexamples. In at least one embodiment, ADAS system 1738 may include,without limitation, any number and combination of anautonomous/adaptive/automatic cruise control (“ACC”) system, acooperative adaptive cruise control (“CACC”) system, a forward crashwarning (“FCW”) system, an automatic emergency braking (“AEB”) system, alane departure warning (“LDW)” system, a lane keep assist (“LKA”)system, a blind spot warning (“BSW”) system, a rear cross-trafficwarning (“RCTW”) system, a collision warning (“CW”) system, a lanecentering (“LC”) system, and/or other systems, features, and/orfunctionality.

In at least one embodiment, ACC system may use RADAR sensor(s) 1760,LIDAR sensor(s) 1764, and/or any number of camera(s). In at least oneembodiment, ACC system may include a longitudinal ACC system and/or alateral ACC system. In at least one embodiment, longitudinal ACC systemmonitors and controls distance to vehicle immediately ahead of vehicle1700 and automatically adjust speed of vehicle 1700 to maintain a safedistance from vehicles ahead. In at least one embodiment, lateral ACCsystem performs distance keeping, and advises vehicle 1700 to changelanes when necessary. In at least one embodiment, lateral ACC is relatedto other ADAS applications such as LC and CW.

In at least one embodiment, CACC system uses information from othervehicles that may be received via network interface 1724 and/or wirelessantenna(s) 1726 from other vehicles via a wireless link, or indirectly,over a network connection (e.g., over Internet). In at least oneembodiment, direct links may be provided by a vehicle-to-vehicle (“V2V”)communication link, while indirect links may be provided by aninfrastructure-to-vehicle (“I2V”) communication link. In general, V2Vcommunication concept provides information about immediately precedingvehicles (e.g., vehicles immediately ahead of and in same lane asvehicle 1700), while I2V communication concept provides informationabout traffic further ahead. In at least one embodiment, CACC system mayinclude either or both I2V and V2V information sources. In at least oneembodiment, given information of vehicles ahead of vehicle 1700, CACCsystem may be more reliable, and it has potential to improve trafficflow smoothness and reduce congestion on a road.

In at least one embodiment, FCW system is designed to alert driver to ahazard, so that driver may take corrective action. In at least oneembodiment, FCW system uses a front-facing camera and/or RADAR sensor(s)1760, coupled to a dedicated processor, DSP, FPGA, and/or ASIC, that iselectrically coupled to driver feedback, such as a display, speaker,and/or vibrating component. In at least one embodiment, FCW system mayprovide a warning, such as in form of a sound, visual warning, vibrationand/or a quick brake pulse.

In at least one embodiment, AEB system detects an impending forwardcollision with another vehicle or other object, and may automaticallyapply brakes if driver does not take corrective action within aspecified time or distance parameter. In at least one embodiment, AEBsystem may use front-facing camera(s) and/or RADAR sensor(s) 1760,coupled to a dedicated processor, DSP, FPGA, and/or ASIC. In at leastone embodiment, when AEB system detects a hazard, AEB system typicallyfirst alerts driver to take corrective action to avoid collision and, ifdriver does not take corrective action, AEB system may automaticallyapply brakes in an effort to prevent, or at least mitigate, impact ofpredicted collision. In at least one embodiment, AEB system, may includetechniques such as dynamic brake support and/or crash imminent braking.

In at least one embodiment, LDW system provides visual, audible, and/ortactile warnings, such as steering wheel or seat vibrations, to alertdriver when vehicle 1700 crosses lane markings. In at least oneembodiment, LDW system does not activate when driver indicates anintentional lane departure, by activating a turn signal. In at least oneembodiment, LDW system may use front-side facing cameras, coupled to adedicated processor, DSP, FPGA, and/or ASIC, that is electricallycoupled to driver feedback, such as a display, speaker, and/or vibratingcomponent. In at least one embodiment, LKA system is a variation of LDWsystem. LKA system provides steering input or braking to correct vehicle1700 if vehicle 1700 starts to exit lane.

In at least one embodiment, BSW system detects and warns driver ofvehicles in an automobile's blind spot. In at least one embodiment, BSWsystem may provide a visual, audible, and/or tactile alert to indicatethat merging or changing lanes is unsafe. In at least one embodiment,BSW system may provide an additional warning when driver uses a turnsignal. In at least one embodiment, BSW system may use rear-side facingcamera(s) and/or RADAR sensor(s) 1760, coupled to a dedicated processor,DSP, FPGA, and/or ASIC, that is electrically coupled to driver feedback,such as a display, speaker, and/or vibrating component.

In at least one embodiment, RCTW system may provide visual, audible,and/or tactile notification when an object is detected outsiderear-camera range when vehicle 1700 is backing up. In at least oneembodiment, RCTW system includes AEB system to ensure that vehiclebrakes are applied to avoid a crash. In at least one embodiment, RCTWsystem may use one or more rear-facing RADAR sensor(s) 1760, coupled toa dedicated processor, DSP, FPGA, and/or ASIC, that is electricallycoupled to driver feedback, such as a display, speaker, and/or vibratingcomponent.

In at least one embodiment, conventional ADAS systems may be prone tofalse positive results which may be annoying and distracting to adriver, but typically are not catastrophic, because conventional ADASsystems alert driver and allow driver to decide whether a safetycondition truly exists and act accordingly. In at least one embodiment,vehicle 1700 itself decides, in case of conflicting results, whether toheed result from a primary computer or a secondary computer (e.g., firstcontroller 1736 or second controller 1736). For example, in at least oneembodiment, ADAS system 1738 may be a backup and/or secondary computerfor providing perception information to a backup computer rationalitymodule. In at least one embodiment, backup computer rationality monitormay run a redundant diverse software on hardware components to detectfaults in perception and dynamic driving tasks. In at least oneembodiment, outputs from ADAS system 1738 may be provided to asupervisory MCU. In at least one embodiment, if outputs from primarycomputer and secondary computer conflict, supervisory MCU determines howto reconcile conflict to ensure safe operation.

In at least one embodiment, primary computer may be configured toprovide supervisory MCU with a confidence score, indicating primarycomputer's confidence in chosen result. In at least one embodiment, ifconfidence score exceeds a threshold, supervisory MCU may follow primarycomputer's direction, regardless of whether secondary computer providesa conflicting or inconsistent result. In at least one embodiment, whereconfidence score does not meet threshold, and where primary andsecondary computer indicate different results (e.g., a conflict),supervisory MCU may arbitrate between computers to determine appropriateoutcome.

In at least one embodiment, supervisory MCU may be configured to run aneural network(s) that is trained and configured to determine, based atleast in part on outputs from primary computer and secondary computer,conditions under which secondary computer provides false alarms. In atleast one embodiment, neural network(s) in supervisory MCU may learnwhen secondary computer's output may be trusted, and when it cannot. Forexample, in at least one embodiment, when secondary computer is aRADAR-based FCW system, a neural network(s) in supervisory MCU may learnwhen FCW system is identifying metallic objects that are not, in fact,hazards, such as a drainage grate or manhole cover that triggers analarm. In at least one embodiment, when secondary computer is acamera-based LDW system, a neural network in supervisory MCU may learnto override LDW when bicyclists or pedestrians are present and a lanedeparture is, in fact, safest maneuver. In at least one embodiment,supervisory MCU may include at least one of a DLA or GPU suitable forrunning neural network(s) with associated memory. In at least oneembodiment, supervisory MCU may comprise and/or be included as acomponent of SoC(s) 1704.

In at least one embodiment, ADAS system 1738 may include a secondarycomputer that performs ADAS functionality using traditional rules ofcomputer vision. In at least one embodiment, secondary computer may useclassic computer vision rules (if-then), and presence of a neuralnetwork(s) in supervisory MCU may improve reliability, safety, andperformance. For example, in at least one embodiment, diverseimplementation and intentional non-identity makes overall system morefault-tolerant, especially to faults caused by software (orsoftware-hardware interface) functionality. For example, in at least oneembodiment, if there is a software bug or error in software running onprimary computer, and non-identical software code running on secondarycomputer provides same overall result, then supervisory MCU may havegreater confidence that overall result is correct, and bug in softwareor hardware on primary computer is not causing material error.

In at least one embodiment, output of ADAS system 1738 may be fed intoprimary computer's perception block and/or primary computer's dynamicdriving task block. For example, in at least one embodiment, if ADASsystem 1738 indicates a forward crash warning due to an objectimmediately ahead, perception block may use this information whenidentifying objects. In at least one embodiment, secondary computer mayhave its own neural network which is trained and thus reduces risk offalse positives, as described herein.

In at least one embodiment, vehicle 1700 may further includeinfotainment SoC 1730 (e.g., an in-vehicle infotainment system (IVI)).Although illustrated and described as an SoC, infotainment system 1730,in at least one embodiment, may not be an SoC, and may include, withoutlimitation, two or more discrete components. In at least one embodiment,infotainment SoC 1730 may include, without limitation, a combination ofhardware and software that may be used to provide audio (e.g., music, apersonal digital assistant, navigational instructions, news, radio,etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g.,hands-free calling), network connectivity (e.g., LTE, WiFi, etc.),and/or information services (e.g., navigation systems, rear-parkingassistance, a radio data system, vehicle related information such asfuel level, total distance covered, brake fuel level, oil level, dooropen/close, air filter information, etc.) to vehicle 1700. For example,infotainment SoC 1730 could include radios, disk players, navigationsystems, video players, USB and Bluetooth connectivity, carputers,in-car entertainment, WiFi, steering wheel audio controls, hands freevoice control, a heads-up display (“HUD”), HMI display 1734, atelematics device, a control panel (e.g., for controlling and/orinteracting with various components, features, and/or systems), and/orother components. In at least one embodiment, infotainment SoC 1730 mayfurther be used to provide information (e.g., visual and/or audible) touser(s) of vehicle, such as information from ADAS system 1738,autonomous driving information such as planned vehicle maneuvers,trajectories, surrounding environment information (e.g., intersectioninformation, vehicle information, road information, etc.), and/or otherinformation.

In at least one embodiment, infotainment SoC 1730 may include any amountand type of GPU functionality. In at least one embodiment, infotainmentSoC 1730 may communicate over bus 1702 (e.g., CAN bus, Ethernet, etc.)with other devices, systems, and/or components of vehicle 1700. In atleast one embodiment, infotainment SoC 1730 may be coupled to asupervisory MCU such that GPU of infotainment system may perform someself-driving functions in event that primary controller(s) 1736 (e.g.,primary and/or backup computers of vehicle 1700) fail. In at least oneembodiment, infotainment SoC 1730 may put vehicle 1700 into a chauffeurto safe stop mode, as described herein.

In at least one embodiment, vehicle 1700 may further include instrumentcluster 1732 (e.g., a digital dash, an electronic instrument cluster, adigital instrument panel, etc.). In at least one embodiment, instrumentcluster 1732 may include, without limitation, a controller and/orsupercomputer (e.g., a discrete controller or supercomputer). In atleast one embodiment, instrument cluster 1732 may include, withoutlimitation, any number and combination of a set of instrumentation suchas a speedometer, fuel level, oil pressure, tachometer, odometer, turnindicators, gearshift position indicator, seat belt warning light(s),parking-brake warning light(s), engine-malfunction light(s),supplemental restraint system (e.g., airbag) information, lightingcontrols, safety system controls, navigation information, etc. In someexamples, information may be displayed and/or shared among infotainmentSoC 1730 and instrument cluster 1732. In at least one embodiment,instrument cluster 1732 may be included as part of infotainment SoC1730, or vice versa. In at least one embodiment, at least one componentshown or described with respect to FIG. 17C is used to implementtechniques and/or functions described in connection with FIGS. 1-15B.

FIG. 17D is a diagram of a system 1777 for communication betweencloud-based server(s) and autonomous vehicle 1700 of FIG. 17A, accordingto at least one embodiment. In at least one embodiment, system 1777 mayinclude, without limitation, server(s) 1778, network(s) 1790, and anynumber and type of vehicles, including vehicle 1700. server(s) 1778 mayinclude, without limitation, a plurality of GPUs 1784(A)-1784(H)(collectively referred to herein as GPUs 1784), PCIe switches1782(A)-1782(H) (collectively referred to herein as PCIe switches 1782),and/or CPUs 1780(A)-1780(B) (collectively referred to herein as CPUs1780). GPUs 1784, CPUs 1780, and PCIe switches 1782 may beinterconnected with high-speed interconnects such as, for example andwithout limitation, NVLink interfaces 1788 developed by NVIDIA and/orPCIe connections 1786. In at least one embodiment, GPUs 1784 areconnected via an NVLink and/or NVSwitch SoC and GPUs 1784 and PCIeswitches 1782 are connected via PCIe interconnects. In at least oneembodiment, although eight GPUs 1784, two CPUs 1780, and four PCIeswitches 1782 are illustrated, this is not intended to be limiting. Inat least one embodiment, each of server(s) 1778 may include, withoutlimitation, any number of GPUs 1784, CPUs 1780, and/or PCIe switches1782, in any combination. For example, in at least one embodiment,server(s) 1778 could each include eight, sixteen, thirty-two, and/ormore GPUs 1784. In at least one embodiment, server(s) 1778 include oneor more CPUs, ASICs, GPUs, FPGAs, systems on chip (SoC), or otherhardware, circuitry, or integrated circuit components that include,e.g., an upscaler or upsampler to upscale an image, a sampler to samplean image (e.g., as part of a DSP), a neural network circuit that isconfigured to perform an upscaler to upscale an image (e.g., from a lowresolution image to a high resolution image), or other hardware tomodify or generate an image, frame, or video to adjust its resolution,size, or pixels; data center server(s) 1778 can use components describedin this disclosure to perform methods, operations, or instructions thatgenerate or modify an image.

In at least one embodiment, server(s) 1778 may receive, over network(s)1790 and from vehicles, image data representative of images showingunexpected or changed road conditions, such as recently commencedroadwork. In at least one embodiment, server(s) 1778 may transmit, overnetwork(s) 1790 and to vehicles, neural networks 1792, updated neuralnetworks 1792, and/or map information 1794, including, withoutlimitation, information regarding traffic and road conditions. In atleast one embodiment, updates to map information 1794 may include,without limitation, updates for HD map 1722, such as informationregarding construction sites, potholes, detours, flooding, and/or otherobstructions. In at least one embodiment, neural networks 1792, updatedneural networks 1792, and/or map information 1794 may have resulted fromnew training and/or experiences represented in data received from anynumber of vehicles in environment, and/or based at least in part ontraining performed at a data center (e.g., using server(s) 1778 and/orother servers).

In at least one embodiment, server(s) 1778 may be used to train machinelearning models (e.g., neural networks) based at least in part ontraining data. In at least one embodiment, training data may begenerated by vehicles, and/or may be generated in a simulation (e.g.,using a game engine). In at least one embodiment, any amount of trainingdata is tagged (e.g., where associated neural network benefits fromsupervised learning) and/or undergoes other pre-processing. In at leastone embodiment, any amount of training data is not tagged and/orpre-processed (e.g., where associated neural network does not requiresupervised learning). In at least one embodiment, once machine learningmodels are trained, machine learning models may be used by vehicles(e.g., transmitted to vehicles over network(s) 1790, and/or machinelearning models may be used by server(s) 1778 to remotely monitorvehicles.

In at least one embodiment, server(s) 1778 may receive data fromvehicles and apply data to up-to-date real-time neural networks forreal-time intelligent inferencing. In at least one embodiment, server(s)1778 may include deep-learning supercomputers and/or dedicated AIcomputers powered by GPU(s) 1784, such as a DGX and DGX Station machinesdeveloped by NVIDIA. However, in at least one embodiment, server(s) 1778may include deep learning infrastructure that use CPU-powered datacenters.

In at least one embodiment, deep-learning infrastructure of server(s)1778 may be capable of fast, real-time inferencing, and may use thatcapability to evaluate and verify health of processors, software, and/orassociated hardware in vehicle 1700. For example, in at least oneembodiment, deep-learning infrastructure may receive periodic updatesfrom vehicle 1700, such as a sequence of images and/or objects thatvehicle 1700 has located in that sequence of images (e.g., via computervision and/or other machine learning object classification techniques).In at least one embodiment, deep-learning infrastructure may run its ownneural network to identify objects and compare them with objectsidentified by vehicle 1700 and, if results do not match anddeep-learning infrastructure concludes that AI in vehicle 1700 ismalfunctioning, then server(s) 1778 may transmit a signal to vehicle1700 instructing a fail-safe computer of vehicle 1700 to assume control,notify passengers, and complete a safe parking maneuver.

In at least one embodiment, server(s) 1778 may include GPU(s) 1784 andone or more programmable inference accelerators (e.g., NVIDIA's TensorRT3). In at least one embodiment, combination of GPU-powered servers andinference acceleration may make real-time responsiveness possible. In atleast one embodiment, such as where performance is less critical,servers powered by CPUs, FPGAs, and other processors may be used forinferencing.

Computer Systems

FIG. 18 is a block diagram illustrating an exemplary computer system,which may be a system with interconnected devices and components, asystem-on-a-chip (SOC) or some combination thereof 1800 formed with aprocessor that may include execution units to execute an instruction,according to at least one embodiment. In at least one embodiment,computer system 1800 may include, without limitation, a component, suchas a processor 1802 to employ execution units including logic to performalgorithms for process data, in accordance with present disclosure, suchas in embodiment described herein. In at least one embodiment, computersystem 1800 may include processors, such as PENTIUM® Processor family,Xeon™, Itanium®, XScale™ and/or StrongARM™, Intel® Core™, or Intel®Nervana™ microprocessors available from Intel Corporation of SantaClara, Calif., although other systems (including PCs having othermicroprocessors, engineering workstations, set-top boxes and like) mayalso be used. In at least one embodiment, computer system 1800 mayexecute a version of WINDOWS' operating system available from MicrosoftCorporation of Redmond, Wash., although other operating systems (UNIXand Linux for example), embedded software, and/or graphical userinterfaces, may also be used.

Embodiments may be used in other devices such as handheld devices andembedded applications. Some examples of handheld devices includecellular phones, Internet Protocol devices, digital cameras, personaldigital assistants (“PDAs”), and handheld PCs. In at least oneembodiment, embedded applications may include a microcontroller, adigital signal processor (“DSP”), system on a chip, network computers(“NetPCs”), set-top boxes, network hubs, wide area network (“WAN”)switches, or any other system that may perform one or more instructionsin accordance with at least one embodiment.

In at least one embodiment, computer system 1800 may include, withoutlimitation, processor 1802 that may include, without limitation, one ormore execution units 1808 to perform machine learning model trainingand/or inferencing according to techniques described herein. In at leastone embodiment, system 18 is a single processor desktop or serversystem, but in another embodiment system 18 may be a multiprocessorsystem. In at least one embodiment, processor 1802 may include, withoutlimitation, a complex instruction set computer (“CISC”) microprocessor,a reduced instruction set computing (“RISC”) microprocessor, a very longinstruction word (“VLIW”) microprocessor, a processor implementing acombination of instruction sets, or any other processor device, such asa digital signal processor, for example. In at least one embodiment,processor 1802 may be coupled to a processor bus 1810 that may transmitdata signals between processor 1802 and other components in computersystem 1800.

In at least one embodiment, processor 1802 may include, withoutlimitation, a Level 1 (“L1”) internal cache memory (“cache”) 1804. In atleast one embodiment, processor 1802 may have a single internal cache ormultiple levels of internal cache. In at least one embodiment, cachememory may reside external to processor 1802. Other embodiments may alsoinclude a combination of both internal and external caches depending onparticular implementation and needs. In at least one embodiment,register file 1806 may store different types of data in variousregisters including, without limitation, integer registers, floatingpoint registers, status registers, and instruction pointer register.

In at least one embodiment, execution unit 1808, including, withoutlimitation, logic to perform integer and floating point operations, alsoresides in processor 1802. In at least one embodiment, processor 1802may also include a microcode (“ucode”) read only memory (“ROM”) thatstores microcode for certain macro instructions. In at least oneembodiment, execution unit 1808 may include logic to handle a packedinstruction set 1809. In at least one embodiment, by including packedinstruction set 1809 in instruction set of a general-purpose processor1802, along with associated circuitry to execute instructions,operations used by many multimedia applications may be performed usingpacked data in a general-purpose processor 1802. In one or moreembodiments, many multimedia applications may be accelerated andexecuted more efficiently by using full width of a processor's data busfor performing operations on packed data, which may eliminate need totransfer smaller units of data across processor's data bus to performone or more operations one data element at a time.

In at least one embodiment, execution unit 1808 may also be used inmicrocontrollers, embedded processors, graphics devices, DSPs, and othertypes of logic circuits. In at least one embodiment, computer system1800 may include, without limitation, a memory 1820. In at least oneembodiment, memory 1820 may be implemented as a Dynamic Random AccessMemory (“DRAM”) device, a Static Random Access Memory (“SRAM”) device,flash memory device, or other memory device. In at least one embodiment,memory 1820 may store instruction(s) 1819 and/or data 1821 representedby data signals that may be executed by processor 1802.

In at least one embodiment, system logic chip may be coupled toprocessor bus 1810 and memory 1820. In at least one embodiment, systemlogic chip may include, without limitation, a memory controller hub(“MCH”) 1816, and processor 1802 may communicate with MCH 1816 viaprocessor bus 1810. In at least one embodiment, MCH 1816 may provide ahigh bandwidth memory path 1818 to memory 1820 for instruction and datastorage and for storage of graphics commands, data, and textures. In atleast one embodiment, MCH 1816 may direct data signals between processor1802, memory 1820, and other components in computer system 1800 and tobridge data signals between processor bus 1810, memory 1820, and asystem I/O 1822. In at least one embodiment, system logic chip mayprovide a graphics port for coupling to a graphics controller. In atleast one embodiment, MCH 1816 may be coupled to memory 1820 through ahigh bandwidth memory path 1818 and graphics/video card 1812 may becoupled to MCH 1816 through an Accelerated Graphics Port (“AGP”)interconnect 1814.

In at least one embodiment, computer system 1800 may use system I/O 1822that is a proprietary hub interface bus to couple MCH 1816 to I/Ocontroller hub (“ICH”) 1830. In at least one embodiment, ICH 1830 mayprovide direct connections to some I/O devices via a local I/O bus. Inat least one embodiment, local I/O bus may include, without limitation,a high-speed I/O bus for connecting peripherals to memory 1820, chipset,and processor 1802. Examples may include, without limitation, an audiocontroller 1829, a firmware hub (“flash BIOS”) 1828, a wirelesstransceiver 1826, a data storage 1824, a legacy I/O controller 1823containing user input and keyboard interfaces, a serial expansion port1827, such as Universal Serial Bus (“USB”), and a network controller1834. In at least one embodiment, data storage 1824 may comprise a harddisk drive, a floppy disk drive, a CD-ROM device, a flash memory device,or other mass storage device.

In at least one embodiment, FIG. 18 illustrates a system, which includesinterconnected hardware devices or “chips”, whereas in otherembodiments, FIG. 18 may illustrate an exemplary System on a Chip(“SoC”). In at least one embodiment, devices illustrated in FIG. 18 maybe interconnected with proprietary interconnects, standardizedinterconnects (e.g., PCIe) or some combination thereof. In at least oneembodiment, one or more components of system 1800 are interconnectedusing compute express link (CXL) interconnects. In at least oneembodiment, one or more components of system 1800 include one or moreCPUs, ASICs, GPUs, FPGAs, or other hardware, circuitry, or integratedcircuit components that include, e.g., an upscaler or upsampler toupscale an image, a sampler to sample an image (e.g., as part of a DSP),a neural network circuit that is configured to perform an upscaler toupscale an image (e.g., from a low resolution image to a high resolutionimage), or other hardware to modify or generate an image, frame, orvideo to adjust its resolution, size, or pixels; one or more componentsof system 1800 can use components described in this disclosure toperform methods, operations, or instructions that generate or modify animage. In at least one embodiment, at least one component shown ordescribed with respect to FIG. 18 is used to implement techniques and/orfunctions described in connection with FIGS. 1-15B.

FIG. 19 is a block diagram illustrating an electronic device 1900 forutilizing a processor 1910, according to at least one embodiment. In atleast one embodiment, electronic device 1900 may be, for example andwithout limitation, a notebook, a tower server, a rack server, a bladeserver, a laptop, a desktop, a tablet, a mobile device, a phone, anembedded computer, or any other suitable electronic device.

In at least one embodiment, system 1900 may include, without limitation,processor 1910 communicatively coupled to any suitable number or kind ofcomponents, peripherals, modules, or devices. In at least oneembodiment, processor 1910 coupled using a bus or interface, such as a1° C. bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus,a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”)bus, a Serial Advance Technology Attachment (“SATA”) bus, a UniversalSerial Bus (“USB”) (versions 1, 2, 3), or a Universal AsynchronousReceiver/Transmitter (“UART”) bus. In at least one embodiment, FIG. 19illustrates a system, which includes interconnected hardware devices or“chips”, whereas in other embodiments, FIG. 19 may illustrate anexemplary System on a Chip (“SoC”). In at least one embodiment, devicesillustrated in FIG. 19 may be interconnected with proprietaryinterconnects, standardized interconnects (e.g., PCIe) or somecombination thereof. In at least one embodiment, one or more componentsof FIG. 19 are interconnected using compute express link (CXL)interconnects.

In at least one embodiment, FIG. 19 may include a display 1924, a touchscreen 1925, a touch pad 1930, a Near Field Communications unit (“NFC”)1945, a sensor hub 1940, a thermal sensor 1946, an Express Chipset(“EC”) 1935, a Trusted Platform Module (“TPM”) 1938, BIOS/firmware/flashmemory (“BIOS, FW Flash”) 1922, a DSP 1960, a drive “SSD or HDD”) 1920such as a Solid State Disk (“SSD”) or a Hard Disk Drive (“HDD”), awireless local area network unit (“WLAN”) 1950, a Bluetooth unit 1952, aWireless Wide Area Network unit (“WWAN”) 1956, a Global PositioningSystem (GPS) 1955, a camera (“USB 3.0 camera”) 1954 such as a USB 3.0camera, or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”)1915 implemented in, for example, LPDDR3 standard. These components mayeach be implemented in any suitable manner.

In at least one embodiment, other components may be communicativelycoupled to processor 1910 through components discussed above. In atleast one embodiment, an accelerometer 1941, Ambient Light Sensor(“ALS”) 1942, compass 1943, and a gyroscope 1944 may be communicativelycoupled to sensor hub 1940. In at least one embodiment, thermal sensor1939, a fan 1937, a keyboard 1946, and a touch pad 1930 may becommunicatively coupled to EC 1935. In at least one embodiment, speaker1963, a headphone 1964, and a microphone (“mic”) 1965 may becommunicatively coupled to an audio unit (“audio codec and class d amp”)1964, which may in turn be communicatively coupled to DSP 1960. In atleast one embodiment, audio unit 1964 may include, for example andwithout limitation, an audio coder/decoder (“codec”) and a class Damplifier. In at least one embodiment, SIM card (“SIM”) 1957 may becommunicatively coupled to WWAN unit 1956. In at least one embodiment,components such as WLAN unit 1950 and Bluetooth unit 1952, as well asWWAN unit 1956 may be implemented in a Next Generation Form Factor(“NGFF”). In at least one embodiment, at least one component shown ordescribed with respect to FIG. 19 is used to implement techniques and/orfunctions described in connection with FIGS. 1-15B.

FIG. 20 illustrates a computer system 2000, according to at least oneembodiment. In at least one embodiment, computer system 2000 isconfigured to implement various processes and methods describedthroughout this disclosure.

In at least one embodiment, computer system 2000 comprises, withoutlimitation, at least one central processing unit (“CPU”) 2002 that isconnected to a communication bus 2010 implemented using any suitableprotocol, such as PCI (“Peripheral Component Interconnect”), peripheralcomponent interconnect express (“PCI-Express”), AGP (“AcceleratedGraphics Port”), HyperTransport, or any other bus or point-to-pointcommunication protocol(s). In at least one embodiment, computer system2000 includes, without limitation, a main memory 2004 and control logic(e.g., implemented as hardware, software, or a combination thereof) anddata are stored in main memory 2004 which may take form of random accessmemory (“RAM”). In at least one embodiment, a network interfacesubsystem (“network interface”) 2022 provides an interface to othercomputing devices and networks for receiving data from and transmittingdata to other systems from computer system 2000.

In at least one embodiment, computer system 2000, in at least oneembodiment, includes, without limitation, input devices 2008, parallelprocessing system 2012, and display devices 2006 which can beimplemented using a conventional cathode ray tube (“CRT”), liquidcrystal display (“LCD”), light emitting diode (“LED”), plasma display,or other suitable display technologies. In at least one embodiment, userinput is received from input devices 2008 such as keyboard, mouse,touchpad, microphone, and more. In at least one embodiment, each offoregoing modules can be situated on a single semiconductor platform toform a processing system. In at least one embodiment, one or morecomponents computer system 2000 can communicate with one or more CPUs,ASICs, GPUs, FPGAs, or other hardware, circuitry, or integrated circuitcomponents that include, e.g., an upscaler or upsampler to upscale animage, a sampler to sample an image (e.g., as part of a DSP), a neuralnetwork circuit that is configured to perform an upscaler to upscale animage (e.g., from a low resolution image to a high resolution image), orother hardware to modify or generate an image, frame, or video to adjustits resolution, size, or pixels; one or more components of computersystem 2000 can use components described in this disclosure to performmethods, operations, or instructions that generate or modify an image.In at least one embodiment, at least one component shown or describedwith respect to FIG. 20 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-15B.

FIG. 21 illustrates a computer system 2100, according to at least oneembodiment. In at least one embodiment, computer system 2100 includes,without limitation, a computer 2110 and a USB stick 2120. In at leastone embodiment, computer 2110 may include, without limitation, anynumber and type of processor(s) (not shown) and a memory (not shown). Inat least one embodiment, computer 2110 includes, without limitation, aserver, a cloud instance, a laptop, and a desktop computer.

In at least one embodiment, USB stick 2120 includes, without limitation,a processing unit 2130, a USB interface 2140, and USB interface logic2150. In at least one embodiment, processing unit 2130 may be anyinstruction execution system, apparatus, or device capable of executinginstructions. In at least one embodiment, processing unit 2130 mayinclude, without limitation, any number and type of processing cores(not shown). In at least one embodiment, processing core 2130 comprisesan application specific integrated circuit (“ASIC”) that is optimized toperform any amount and type of operations associated with machinelearning. For instance, in at least one embodiment, processing core 2130is a tensor processing unit (“TPC”) that is optimized to perform machinelearning inference operations. In at least one embodiment, processingcore 2130 is a vision processing unit (“VPU”) that is optimized toperform machine vision and machine learning inference operations.

In at least one embodiment, USB interface 2140 may be any type of USBconnector or USB socket. For instance, in at least one embodiment, USBinterface 2140 is a USB 3.0 Type-C socket for data and power. In atleast one embodiment, USB interface 2140 is a USB 3.0 Type-A connector.In at least one embodiment, USB interface logic 2150 may include anyamount and type of logic that enables processing unit 2130 to interfacewith or devices (e.g., computer 2110) via USB connector 2140.

In at least one embodiment, one or more components of processing core2130 can communicate with one or more CPUs, ASICs, GPUs, FPGAs, or otherhardware, circuitry, or integrated circuit components that include,e.g., an upscaler or upsampler to upscale an image, a sampler to samplean image (e.g., as part of a DSP), a neural network circuit that isconfigured to perform an upscaler to upscale an image (e.g., from a lowresolution image to a high resolution image), or other hardware tomodify or generate an image, frame, or video to adjust its resolution,size, or pixels; one or more components of processing core 2130 can usecomponents described in this disclosure to perform methods, operations,or instructions that generate or modify an image. In at least oneembodiment, at least one component shown or described with respect toFIG. 21 is used to implement techniques and/or functions described inconnection with FIGS. 1-15B.

FIG. 22A illustrates an exemplary architecture in which a plurality ofGPUs 2210-2213 is communicatively coupled to a plurality of multi-coreprocessors 2205-2206 over high-speed links 2240-2243 (e.g., buses,point-to-point interconnects, etc.). In one embodiment, high-speed links2240-2243 support a communication throughput of 4 GB/s, 30 GB/s, 80 GB/sor higher. Various interconnect protocols may be used including, but notlimited to, PCIe 4.0 or 5.0 and NVLink 2.0.

In addition, and in one embodiment, two or more of GPUs 2210-2213 areinterconnected over high-speed links 2229-2230, which may be implementedusing same or different protocols/links than those used for high-speedlinks 2240-2243. Similarly, two or more of multi-core processors2205-2206 may be connected over high-speed link 2228 which may besymmetric multi-processor (SMP) buses operating at 20 GB/s, 30 GB/s, 120GB/s or higher. Alternatively, all communication between various systemcomponents shown in FIG. 22A may be accomplished using sameprotocols/links (e.g., over a common interconnection fabric).

In one embodiment, each multi-core processor 2205-2206 iscommunicatively coupled to a processor memory 2201-2202, via memoryinterconnects 2226-2227, respectively, and each GPU 2210-2213 iscommunicatively coupled to GPU memory 2220-2223 over GPU memoryinterconnects 2250-2253, respectively. Memory interconnects 2226-2227and 2250-2253 may utilize same or different memory access technologies.By way of example, and not limitation, processor memories 2201-2202 andGPU memories 2220-2223 may be volatile memories such as dynamic randomaccess memories (DRAMs) (including stacked DRAMs), Graphics DDR SDRAM(GDDR) (e.g., GDDR5, GDDR6), or High Bandwidth Memory (HBM) and/or maybe non-volatile memories such as 3D XPoint or Nano-Ram. In oneembodiment, some portion of processor memories 2201-2202 may be volatilememory and another portion may be non-volatile memory (e.g., using atwo-level memory (2LM) hierarchy).

As described herein, although various processors 2205-2206 and GPUs2210-2213 may be physically coupled to a particular memory 2201-2202,2220-2223, respectively, a unified memory architecture may beimplemented in which a same virtual system address space (also referredto as “effective address” space) is distributed among various physicalmemories. For example, processor memories 2201-2202 may each comprise 64GB of system memory address space and GPU memories 2220-2223 may eachcomprise 32 GB of system memory address space (resulting in a total of256 GB addressable memory in this example).

FIG. 22B illustrates additional details for an interconnection between amulti-core processor 2207 and a graphics acceleration module 2246 inaccordance with one exemplary embodiment. Graphics acceleration module2246 may include one or more GPU chips integrated on a line card whichis coupled to processor 2207 via high-speed link 2240. Alternatively,graphics acceleration module 2246 may be integrated on a same package orchip as processor 2207.

In at least one embodiment, illustrated processor 2207 includes aplurality of cores 2260A-2260D, each with a translation lookaside buffer2261A-2261D and one or more caches 2262A-2262D. In at least oneembodiment, cores 2260A-2260D may include various other components forexecuting instructions and processing data which are not illustrated.Caches 2262A-2262D may comprise level 1 (L1) and level 2 (L2) caches. Inaddition, one or more shared caches 2256 may be included in caches2262A-2262D and shared by sets of cores 2260A-2260D. For example, oneembodiment of processor 2207 includes 24 cores, each with its own L1cache, twelve shared L2 caches, and twelve shared L3 caches. In thisembodiment, one or more L2 and L3 caches are shared by two adjacentcores. Processor 2207 and graphics acceleration module 2246 connect withsystem memory 2214, which may include processor memories 2201-2202 ofFIG. 22A.

Coherency is maintained for data and instructions stored in variouscaches 2262A-2262D, 2256 and system memory 2214 via inter-corecommunication over a coherence bus 2264. For example, each cache mayhave cache coherency logic/circuitry associated therewith to communicateto over coherence bus 2264 in response to detected reads or writes toparticular cache lines. In one implementation, a cache snooping protocolis implemented over coherence bus 2264 to snoop cache accesses.

In one embodiment, a proxy circuit 2225 communicatively couples graphicsacceleration module 2246 to coherence bus 2264, allowing graphicsacceleration module 2246 to participate in a cache coherence protocol asa peer of cores 2260A-2260D. An interface 2235 provides connectivity toproxy circuit 2225 over high-speed link 2240 (e.g., a PCIe bus, NVLink,etc.) and an interface 2237 connects graphics acceleration module 2246to link 2240.

In one implementation, an accelerator integration circuit 2236 providescache management, memory access, context management, and interruptmanagement services on behalf of a plurality of graphics processingengines 2231, 2232, N of graphics acceleration module 2246. Graphicsprocessing engines 2231, 2232, N may each comprise a separate graphicsprocessing unit (GPU). Alternatively, graphics processing engines 2231,2232, N may comprise different types of graphics processing engineswithin a GPU such as graphics execution units, media processing engines(e.g., video encoders/decoders), samplers, and blit engines. In at leastone embodiment, graphics acceleration module 2246 may be a GPU with aplurality of graphics processing engines 2231-2232, N or graphicsprocessing engines 2231-2232, N may be individual GPUs integrated on acommon package, line card, or chip.

In one embodiment, accelerator integration circuit 2236 includes amemory management unit (MMU) 2239 for performing various memorymanagement functions such as virtual-to-physical memory translations(also referred to as effective-to-real memory translations) and memoryaccess protocols for accessing system memory 2214. MMU 2239 may alsoinclude a translation lookaside buffer (TLB) (not shown) for cachingvirtual/effective to physical/real address translations. In oneimplementation, a cache 2238 stores commands and data for efficientaccess by graphics processing engines 2231-2232, N. In one embodiment,data stored in cache 2238 and graphics memories 2233-2234, M is keptcoherent with core caches 2262A-2262D, 2256 and system memory 2214. Asmentioned, this may be accomplished via proxy circuit 2225 on behalf ofcache 2238 and memories 2233-2234, M (e.g., sending updates to cache2238 related to modifications/accesses of cache lines on processorcaches 2262A-2262D, 2256 and receiving updates from cache 2238).

A set of registers 2245 store context data for threads executed bygraphics processing engines 2231-2232, N and a context managementcircuit 2248 manages thread contexts. For example, context managementcircuit 2248 may perform save and restore operations to save and restorecontexts of various threads during contexts switches (e.g., where afirst thread is saved and a second thread is stored so that a secondthread can be execute by a graphics processing engine). For example, ona context switch, context management circuit 2248 may store currentregister values to a designated region in memory (e.g., identified by acontext pointer). It may then restore register values when returning toa context. In one embodiment, an interrupt management circuit 2247receives and processes interrupts received from system devices.

In one implementation, virtual/effective addresses from a graphicsprocessing engine 2231 are translated to real/physical addresses insystem memory 2214 by MMU 2239. One embodiment of acceleratorintegration circuit 2236 supports multiple (e.g., 4, 8, 16) graphicsaccelerator modules 2246 and/or other accelerator devices. Graphicsaccelerator module 2246 may be dedicated to a single applicationexecuted on processor 2207 or may be shared between multipleapplications. In one embodiment, a virtualized graphics executionenvironment is presented in which resources of graphics processingengines 2231-2232, N are shared with multiple applications or virtualmachines (VMs). In at least one embodiment, resources may be subdividedinto “slices” which are allocated to different VMs and/or applicationsbased on processing requirements and priorities associated with VMsand/or applications.

In at least one embodiment, accelerator integration circuit 2236performs as a bridge to a system for graphics acceleration module 2246and provides address translation and system memory cache services. Inaddition, accelerator integration circuit 2236 may providevirtualization facilities for a host processor to manage virtualizationof graphics processing engines 2231-2232, interrupts, and memorymanagement.

Because hardware resources of graphics processing engines 2231-2232, Nare mapped explicitly to a real address space seen by host processor2207, any host processor can address these resources directly using aneffective address value. One function of accelerator integration circuit2236, in one embodiment, is physical separation of graphics processingengines 2231-2232, N so that they appear to a system as independentunits.

In at least one embodiment, one or more graphics memories 2233-2234, Mare coupled to each of graphics processing engines 2231-2232, N,respectively. Graphics memories 2233-2234, M store instructions and databeing processed by each of graphics processing engines 2231-2232, N.Graphics memories 2233-2234, M may be volatile memories such as DRAMs(including stacked DRAMs), GDDR memory (e.g., GDDR5, GDDR6), or HBM,and/or may be non-volatile memories such as 3D XPoint or Nano-Ram.

In one embodiment, to reduce data traffic over link 2240, biasingtechniques are used to ensure that data stored in graphics memories2233-2234, M is data which will be used most frequently by graphicsprocessing engines 2231-2232, N and preferably not used by cores2260A-2260D (at least not frequently). Similarly, a biasing mechanismattempts to keep data needed by cores (and preferably not graphicsprocessing engines 2231-2232, N) within caches 2262A-2262D, 2256 ofcores and system memory 2214.

FIG. 22C illustrates another exemplary embodiment in which acceleratorintegration circuit 2236 is integrated within processor 2207. In thisembodiment, graphics processing engines 2231-2232, N communicatedirectly over high-speed link 2240 to accelerator integration circuit2236 via interface 2237 and interface 2235 (which, again, may be utilizeany form of bus or interface protocol). Accelerator integration circuit2236 may perform same operations as those described with respect to FIG.22B, but potentially at a higher throughput given its close proximity tocoherence bus 2264 and caches 2262A-2262D, 2256. One embodiment supportsdifferent programming models including a dedicated-process programmingmodel (no graphics acceleration module virtualization) and sharedprogramming models (with virtualization), which may include programmingmodels which are controlled by accelerator integration circuit 2236 andprogramming models which are controlled by graphics acceleration module2246.

In at least one embodiment, graphics processing engines 2231-2232, N arededicated to a single application or process under a single operatingsystem. In at least one embodiment, a single application can funnelother application requests to graphics processing engines 2231-2232, N,providing virtualization within a VM/partition.

In at least one embodiment, graphics processing engines 2231-2232, N,may be shared by multiple VM/application partitions. In at least oneembodiment, shared models may use a system hypervisor to virtualizegraphics processing engines 2231-2232, N to allow access by eachoperating system. For single-partition systems without a hypervisor,graphics processing engines 2231-2232, N are owned by an operatingsystem. In at least one embodiment, an operating system can virtualizegraphics processing engines 2231-2232, N to provide access to eachprocess or application.

In at least one embodiment, graphics acceleration module 2246 or anindividual graphics processing engine 2231-2232, N selects a processelement using a process handle. In one embodiment, process elements arestored in system memory 2214 and are addressable using an effectiveaddress to real address translation techniques described herein. In atleast one embodiment, a process handle may be an implementation-specificvalue provided to a host process when registering its context withgraphics processing engine 2231-2232, N (that is, calling systemsoftware to add a process element to a process element linked list). Inat least one embodiment, a lower 16-bits of a process handle may be anoffset of the process element within a process element linked list.

FIG. 22D illustrates an exemplary accelerator integration slice 2290. Asused herein, a “slice” comprises a specified portion of processingresources of accelerator integration circuit 2236. Application effectiveaddress space 2282 within system memory 2214 stores process elements2283. In one embodiment, process elements 2283 are stored in response toGPU invocations 2281 from applications 2280 executed on processor 2207.A process element 2283 contains process state for correspondingapplication 2280. A work descriptor (WD) 2284 contained in processelement 2283 can be a single job requested by an application or maycontain a pointer to a queue of jobs. In at least one embodiment, WD2284 is a pointer to a job request queue in an application's addressspace 2282.

Graphics acceleration module 2246 and/or individual graphics processingengines 2231-2232, N can be shared by all or a subset of processes in asystem. In at least one embodiment, an infrastructure for setting upprocess state and sending a WD 2284 to a graphics acceleration module2246 to start a job in a virtualized environment may be included.

In at least one embodiment, a dedicated-process programming model isimplementation-specific. In this model, a single process owns graphicsacceleration module 2246 or an individual graphics processing engine2231. Because graphics acceleration module 2246 is owned by a singleprocess, a hypervisor initializes accelerator integration circuit 2236for an owning partition and an operating system initializes acceleratorintegration circuit 2236 for an owning process when graphicsacceleration module 2246 is assigned.

In operation, a WD fetch unit 2291 in accelerator integration slice 2290fetches next WD 2284 which includes an indication of work to be done byone or more graphics processing engines of graphics acceleration module2246. Data from WD 2284 may be stored in registers 2245 and used by MMU2239, interrupt management circuit 2247 and/or context managementcircuit 2248 as illustrated. For example, one embodiment of MMU 2239includes segment/page walk circuitry for accessing segment/page tables2286 within OS virtual address space 2285. Interrupt management circuit2247 may process interrupt events 2292 received from graphicsacceleration module 2246. When performing graphics operations, aneffective address 2293 generated by a graphics processing engine2231-2232, N is translated to a real address by MMU 2239.

In one embodiment, a same set of registers 2245 are duplicated for eachgraphics processing engine 2231-2232, N and/or graphics accelerationmodule 2246 and may be initialized by a hypervisor or operating system.Each of these duplicated registers may be included in an acceleratorintegration slice 2290. Exemplary registers that may be initialized by ahypervisor are shown in Table 1.

TABLE 1 Hypervisor Initialized Registers 1 Slice Control Register 2 RealAddress (RA) Scheduled Processes Area Pointer 3 Authority Mask OverrideRegister 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector TableEntry Limit 6 State Register 7 Logical Partition ID 8 Real address (RA)Hypervisor Accelerator Utilization Record Pointer 9 Storage DescriptionRegister

Exemplary registers that may be initialized by an operating system areshown in Table 2.

TABLE 2 Operating System Initialized Registers 1 Process and ThreadIdentification 2 Effective Address (EA) Context Save/Restore Pointer 3Virtual Address (VA) Accelerator Utilization Record Pointer 4 VirtualAddress (VA) Storage Segment Table Pointer 5 Authority Mask 6 Workdescriptor

In one embodiment, each WD 2284 is specific to a particular graphicsacceleration module 2246 and/or graphics processing engines 2231-2232,N. It contains all information required by a graphics processing engine2231-2232, N to do work or it can be a pointer to a memory locationwhere an application has set up a command queue of work to be completed.

FIG. 22E illustrates additional details for one exemplary embodiment ofa shared model. This embodiment includes a hypervisor real address space2298 in which a process element list 2299 is stored. Hypervisor realaddress space 2298 is accessible via a hypervisor 2296 which virtualizesgraphics acceleration module engines for operating system 2295.

In at least one embodiment, shared programming models allow for all or asubset of processes from all or a subset of partitions in a system touse a graphics acceleration module 2246. There are two programmingmodels where graphics acceleration module 2246 is shared by multipleprocesses and partitions: time-sliced shared and graphics directedshared.

In this model, system hypervisor 2296 owns graphics acceleration module2246 and makes its function available to all operating systems 2295. Fora graphics acceleration module 2246 to support virtualization by systemhypervisor 2296, graphics acceleration module 2246 may adhere to thefollowing: 1) An application's job request must be autonomous (that is,state does not need to be maintained between jobs), or graphicsacceleration module 2246 must provide a context save and restoremechanism. 2) An application's job request is guaranteed by graphicsacceleration module 2246 to complete in a specified amount of time,including any translation faults, or graphics acceleration module 2246provides an ability to preempt processing of a job. 3) Graphicsacceleration module 2246 must be guaranteed fairness between processeswhen operating in a directed shared programming model.

In at least one embodiment, application 2280 is required to make anoperating system 2295 system call with a graphics acceleration module2246 type, a work descriptor (WD), an authority mask register (AMR)value, and a context save/restore area pointer (CSRP). In at least oneembodiment, graphics acceleration module 2246 type describes a targetedacceleration function for a system call. In at least one embodiment,graphics acceleration module 2246 type may be a system-specific value.In at least one embodiment, WD is formatted specifically for graphicsacceleration module 2246 and can be in a form of a graphics accelerationmodule 2246 command, an effective address pointer to a user-definedstructure, an effective address pointer to a queue of commands, or anyother data structure to describe work to be done by graphicsacceleration module 2246. In one embodiment, an AMR value is an AMRstate to use for a current process. In at least one embodiment, a valuepassed to an operating system is similar to an application setting anAMR. If accelerator integration circuit 2236 and graphics accelerationmodule 2246 implementations do not support a User Authority MaskOverride Register (UAMOR), an operating system may apply a current UAMORvalue to an AMR value before passing an AMR in a hypervisor call.Hypervisor 2296 may optionally apply a current Authority Mask OverrideRegister (AMOR) value before placing an AMR into process element 2283.In at least one embodiment, CSRP is one of registers 2245 containing aneffective address of an area in an application's address space 2282 forgraphics acceleration module 2246 to save and restore context state.This pointer is optional if no state is required to be saved betweenjobs or when a job is preempted. In at least one embodiment, contextsave/restore area may be pinned system memory.

Upon receiving a system call, operating system 2295 may verify thatapplication 2280 has registered and been given authority to use graphicsacceleration module 2246. Operating system 2295 then calls hypervisor2296 with information shown in Table 3.

TABLE 3 OS to Hypervisor Call Parameters 1 A work descriptor (WD) 2 AnAuthority Mask Register (AMR) value (potentially masked) 3 An effectiveaddress (EA) Context Save/Restore Area Pointer (CSRP) 4 A process ID(PID) and optional thread ID (TID) 5 A virtual address (VA) acceleratorutilization record pointer (AURP) 6 Virtual address of storage segmenttable pointer (SSTP) 7 A logical interrupt service number (LISN)

Upon receiving a hypervisor call, hypervisor 2296 verifies thatoperating system 2295 has registered and been given authority to usegraphics acceleration module 2246. Hypervisor 2296 then puts processelement 2283 into a process element linked list for a correspondinggraphics acceleration module 2246 type. A process element may includeinformation shown in Table 4.

TABLE 4 Process Element Information 1 A work descriptor (WD) 2 AnAuthority Mask Register (AMR) value (potentially masked). 3 An effectiveaddress (EA) Context Save/Restore Area Pointer (CSRP) 4 A process ID(PID) and optional thread ID (TID) 5 A virtual address (VA) acceleratorutilization record pointer (AURP) 6 Virtual address of storage segmenttable pointer (SSTP) 7 A logical interrupt service number (LISN) 8Interrupt vector table, derived from hypervisor call parameters 9 Astate register (SR) value 10 A logical partition ID (LPID) 11 A realaddress (RA) hypervisor accelerator utilization record pointer 12Storage Descriptor Register (SDR)

In at least one embodiment, hypervisor initializes a plurality ofaccelerator integration slice 2290 registers 2245.

As illustrated in FIG. 22F, in at least one embodiment, a unified memoryis used, addressable via a common virtual memory address space used toaccess physical processor memories 2201-2202 and GPU memories 2220-2223.In this implementation, operations executed on GPUs 2210-2213 utilize asame virtual/effective memory address space to access processor memories2201-2202 and vice versa, thereby simplifying programmability. In oneembodiment, a first portion of a virtual/effective address space isallocated to processor memory 2201, a second portion to second processormemory 2202, a third portion to GPU memory 2220, and so on. In at leastone embodiment, an entire virtual/effective memory space (sometimesreferred to as an effective address space) is thereby distributed acrosseach of processor memories 2201-2202 and GPU memories 2220-2223,allowing any processor or GPU to access any physical memory with avirtual address mapped to that memory.

In one embodiment, bias/coherence management circuitry 2294A-2294Ewithin one or more of MMUs 2239A-2239E ensures cache coherence betweencaches of one or more host processors (e.g., 2205) and GPUs 2210-2213and implements biasing techniques indicating physical memories in whichcertain types of data should be stored. While multiple instances ofbias/coherence management circuitry 2294A-2294E are illustrated in FIG.22F, bias/coherence circuitry may be implemented within an MMU of one ormore host processors 2205 and/or within accelerator integration circuit2236.

One embodiment allows GPU-attached memory 2220-2223 to be mapped as partof system memory, and accessed using shared virtual memory (SVM)technology, but without suffering performance drawbacks associated withfull system cache coherence. In at least one embodiment, an ability forGPU-attached memory 2220-2223 to be accessed as system memory withoutonerous cache coherence overhead provides a beneficial operatingenvironment for GPU offload. This arrangement allows host processor 2205software to setup operands and access computation results, withoutoverhead of tradition I/O DMA data copies. Such traditional copiesinvolve driver calls, interrupts and memory mapped I/O (MMIO) accessesthat are all inefficient relative to simple memory accesses. In at leastone embodiment, an ability to access GPU attached memory 2220-2223without cache coherence overheads can be critical to execution time ofan offloaded computation. In cases with substantial streaming writememory traffic, for example, cache coherence overhead can significantlyreduce an effective write bandwidth seen by a GPU 2210-2213. In at leastone embodiment, efficiency of operand setup, efficiency of resultsaccess, and efficiency of GPU computation may play a role in determiningeffectiveness of a GPU offload.

In at least one embodiment, selection of GPU bias and host processorbias is driven by a bias tracker data structure. A bias table may beused, for example, which may be a page-granular structure (i.e.,controlled at a granularity of a memory page) that includes 1 or 2 bitsper GPU-attached memory page. In at least one embodiment, a bias tablemay be implemented in a stolen memory range of one or more GPU-attachedmemories 2220-2223, with or without a bias cache in GPU 2210-2213 (e.g.,to cache frequently/recently used entries of a bias table).Alternatively, an entire bias table may be maintained within a GPU.

In at least one embodiment, a bias table entry associated with eachaccess to GPU-attached memory 2220-2223 is accessed prior to actualaccess to a GPU memory, causing the following operations. First, localrequests from GPU 2210-2213 that find their page in GPU bias areforwarded directly to a corresponding GPU memory 2220-2223. Localrequests from a GPU that find their page in host bias are forwarded toprocessor 2205 (e.g., over a high-speed link as discussed above). In oneembodiment, requests from processor 2205 that find a requested page inhost processor bias complete a request like a normal memory read.Alternatively, requests directed to a GPU-biased page may be forwardedto GPU 2210-2213. In at least one embodiment, a GPU may then transitiona page to a host processor bias if it is not currently using a page. Inat least one embodiment, bias state of a page can be changed either by asoftware-based mechanism, a hardware-assisted software-based mechanism,or, for a limited set of cases, a purely hardware-based mechanism.

One mechanism for changing bias state employs an API call (e.g.,OpenCL), which, in turn, calls a GPU's device driver which, in turn,sends a message (or enqueues a command descriptor) to a GPU directing itto change a bias state and, for some transitions, perform a cacheflushing operation in a host. In at least one embodiment, cache flushingoperation is used for a transition from host processor 2205 bias to GPUbias, but is not for an opposite transition.

In one embodiment, cache coherency is maintained by temporarilyrendering GPU-biased pages uncacheable by host processor 2205. To accessthese pages, processor 2205 may request access from GPU 2210 which mayor may not grant access right away. Thus, to reduce communicationbetween processor 2205 and GPU 2210 it is beneficial to ensure thatGPU-biased pages are those which are required by a GPU but not hostprocessor 2205 and vice versa.

FIG. 23 illustrates exemplary integrated circuits and associatedgraphics processors that may be fabricated using one or more IP cores,according to various embodiments described herein. In addition to whatis illustrated, other logic and circuits may be included in at least oneembodiment, including additional graphics processors/cores, peripheralinterface controllers, or general-purpose processor cores.

FIG. 23 is a block diagram illustrating an exemplary system on a chipintegrated circuit 2300 that may be fabricated using one or more IPcores, according to at least one embodiment. In at least one embodiment,integrated circuit 2300 includes one or more application processor(s)2305 (e.g., CPUs), at least one graphics processor 2310, and mayadditionally include an image processor 2315 and/or a video processor2320, any of which may be a modular IP core. In at least one embodiment,integrated circuit 2300 includes peripheral or bus logic including a USBcontroller 2325, UART controller 2330, an SPI/SDIO controller 2335, andan I.sup.2S/I.sup.2C controller 2340. In at least one embodiment,integrated circuit 2300 can include a display device 2345 coupled to oneor more of a high-definition multimedia interface (HDMI) controller 2350and a mobile industry processor interface (MIPI) display interface 2355.In at least one embodiment, storage may be provided by a flash memorysubsystem 2360 including flash memory and a flash memory controller. Inat least one embodiment, memory interface may be provided via a memorycontroller 2365 for access to SDRAM or SRAM memory devices. In at leastone embodiment, some integrated circuits additionally include anembedded security engine 2370. In at least one embodiment, at least onecomponent shown or described with respect to FIG. 23 is used toimplement techniques and/or functions described in connection with FIGS.1-15B.

FIGS. 24A-24B illustrate exemplary integrated circuits and associatedgraphics processors that may be fabricated using one or more IP cores,according to various embodiments described herein. In addition to whatis illustrated, other logic and circuits may be included in at least oneembodiment, including additional graphics processors/cores, peripheralinterface controllers, or general-purpose processor cores.

FIGS. 24A-24B are block diagrams illustrating exemplary graphicsprocessors for use within an SoC, according to embodiments describedherein. FIG. 24A illustrates an exemplary graphics processor 2410 of asystem on a chip integrated circuit that may be fabricated using one ormore IP cores, according to at least one embodiment. FIG. 24Billustrates an additional exemplary graphics processor 2440 of a systemon a chip integrated circuit that may be fabricated using one or more IPcores, according to at least one embodiment. In at least one embodiment,graphics processor 2410 of FIG. 24A is a low power graphics processorcore. In at least one embodiment, graphics processor 2440 of FIG. 24B isa higher performance graphics processor core. In at least oneembodiment, each of graphics processors 2410, 2440 can be variants ofgraphics processor 2310 of FIG. 23 .

In at least one embodiment, graphics processor 2410 includes a vertexprocessor 2405 and one or more fragment processor(s) 2415A-2415N (e.g.,2415A, 2415B, 2415C, 2415D, through 2415N-1, and 2415N). In at least oneembodiment, graphics processor 2410 can execute different shaderprograms via separate logic, such that vertex processor 2405 isoptimized to execute operations for vertex shader programs, while one ormore fragment processor(s) 2415A-2415N execute fragment (e.g., pixel)shading operations for fragment or pixel shader programs. In at leastone embodiment, vertex processor 2405 performs a vertex processing stageof a 3D graphics pipeline and generates primitives and vertex data. Inat least one embodiment, fragment processor(s) 2415A-2415N use primitiveand vertex data generated by vertex processor 2405 to produce aframebuffer that is displayed on a display device. In at least oneembodiment, fragment processor(s) 2415A-2415N are optimized to executefragment shader programs as provided for in an OpenGL API, which may beused to perform similar operations as a pixel shader program as providedfor in a Direct 3D API.

In at least one embodiment, graphics processor 2410 additionallyincludes one or more memory management units (MMUs) 2420A-2420B,cache(s) 2425A-2425B, and circuit interconnect(s) 2430A-2430B. In atleast one embodiment, one or more MMU(s) 2420A-2420B provide for virtualto physical address mapping for graphics processor 2410, including forvertex processor 2405 and/or fragment processor(s) 2415A-2415N, whichmay reference vertex or image/texture data stored in memory, in additionto vertex or image/texture data stored in one or more cache(s)2425A-2425B. In at least one embodiment, one or more MMU(s) 2420A-2420Bmay be synchronized with other MMUs within system, including one or moreMMUs associated with one or more application processor(s) 2305, imageprocessors 2315, and/or video processors 2320 of FIG. 23 , such thateach processor 2305-2320 can participate in a shared or unified virtualmemory system. In at least one embodiment, one or more circuitinterconnect(s) 2430A-2430B enable graphics processor 2410 to interfacewith other IP cores within SoC, either via an internal bus of SoC or viaa direct connection.

In at least one embodiment, graphics processor 2440 includes one or moreMMU(s) 2420A-2420B, caches 2425A-2425B, and circuit interconnects2430A-2430B of graphics processor 2410 of FIG. 24A. In at least oneembodiment, graphics processor 2440 includes one or more shader core(s)2455A-2455N (e.g., 2455A, 2455B, 2455C, 2455D, 2455E, 2455F, through2455N-1, and 2455N), which provides for a unified shader corearchitecture in which a single core or type or core can execute alltypes of programmable shader code, including shader program code toimplement vertex shaders, fragment shaders, and/or compute shaders. Inat least one embodiment, a number of shader cores can vary. In at leastone embodiment, graphics processor 2440 includes an inter-core taskmanager 2445, which acts as a thread dispatcher to dispatch executionthreads to one or more shader cores 2455A-2455N and a tiling unit 2458to accelerate tiling operations for tile-based rendering, in whichrendering operations for a scene are subdivided in image space, forexample to exploit local spatial coherence within a scene or to optimizeuse of internal caches.

In at least one embodiment, at least one component shown or describedwith respect to FIGS. 24A-24B is used to implement techniques and/orfunctions described in connection with FIGS. 1-15B.

FIGS. 25A-25B illustrate additional exemplary graphics processor logicaccording to embodiments described herein. FIG. 25A illustrates agraphics core 2500 that may be included within graphics processor 2310of FIG. 23 , in at least one embodiment, and may be a unified shadercore 2455A-2455N as in FIG. 24B in at least one embodiment. FIG. 25Billustrates a highly-parallel general-purpose graphics processing unit2530 suitable for deployment on a multi-chip module in at least oneembodiment.

In at least one embodiment, graphics core 2500 includes a sharedinstruction cache 2502, a texture unit 2518, and a cache/shared memory2520 that are common to execution resources within graphics core 2500.In at least one embodiment, graphics core 2500 can include multipleslices 2501A-2501N or partition for each core, and a graphics processorcan include multiple instances of graphics core 2500. Slices 2501A-2501Ncan include support logic including a local instruction cache2504A-2504N, a thread scheduler 2506A-2506N, a thread dispatcher2508A-2508N, and a set of registers 2510A-2510N. In at least oneembodiment, slices 2501A-2501N can include a set of additional functionunits (AFUs 2512A-2512N), floating-point units (FPU 2514A-2514N),integer arithmetic logic units (ALUs 2516-2516N), address computationalunits (ACU 2513A-2513N), double-precision floating-point units (DPFPU2515A-2515N), and matrix processing units (MPU 2517A-2517N).

In at least one embodiment, FPUs 2514A-2514N can performsingle-precision (32-bit) and half-precision (16-bit) floating pointoperations, while DPFPUs 2515A-2515N perform double precision (64-bit)floating point operations. In at least one embodiment, ALUs 2516A-2516Ncan perform variable precision integer operations at 8-bit, 16-bit, and32-bit precision, and can be configured for mixed precision operations.In at least one embodiment, MPUs 2517A-2517N can also be configured formixed precision matrix operations, including half-precision floatingpoint and 8-bit integer operations. In at least one embodiment, MPUs2517-2517N can perform a variety of matrix operations to acceleratemachine learning application frameworks, including enabling support foraccelerated general matrix to matrix multiplication (GEMM). In at leastone embodiment, AFUs 2512A-2512N can perform additional logic operationsnot supported by floating-point or integer units, includingtrigonometric operations (e.g., Sine, Cosine, etc.).

In at least one embodiment, at least one component shown or describedwith respect to FIG. 25A is used to implement techniques and/orfunctions described in connection with FIGS. 1-15B.

FIG. 25B illustrates a general-purpose processing unit (GPGPU) 2530 thatcan be configured to enable highly-parallel compute operations to beperformed by an array of graphics processing units, in at least oneembodiment. In at least one embodiment, GPGPU 2530 can be linkeddirectly to other instances of GPGPU 2530 to create a multi-GPU clusterto improve training speed for deep neural networks. In at least oneembodiment, GPGPU 2530 includes a host interface 2532 to enable aconnection with a host processor. In at least one embodiment, hostinterface 2532 is a PCI Express interface. In at least one embodiment,host interface 2532 can be a vendor specific communications interface orcommunications fabric. In at least one embodiment, GPGPU 2530 receivescommands from a host processor and uses a global scheduler 2534 todistribute execution threads associated with those commands to a set ofcompute clusters 2536A-2536H. In at least one embodiment, computeclusters 2536A-2536H share a cache memory 2538. In at least oneembodiment, cache memory 2538 can serve as a higher-level cache forcache memories within compute clusters 2536A-2536H.

In at least one embodiment, GPGPU 2530 includes memory 2544A-2544Bcoupled with compute clusters 2536A-2536H via a set of memorycontrollers 2542A-2542B. In at least one embodiment, memory 2544A-2544Bcan include various types of memory devices including dynamic randomaccess memory (DRAM) or graphics random access memory, such assynchronous graphics random access memory (SGRAM), including graphicsdouble data rate (GDDR) memory.

In at least one embodiment, compute clusters 2536A-2536H each include aset of graphics cores, such as graphics core 2500 of FIG. 25A, which caninclude multiple types of integer and floating point logic units thatcan perform computational operations at a range of precisions includingsuited for machine learning computations. For example, in at least oneembodiment, at least a subset of floating point units in each of computeclusters 2536A-2536H can be configured to perform 16-bit or 32-bitfloating point operations, while a different subset of floating pointunits can be configured to perform 64-bit floating point operations.

In at least one embodiment, multiple instances of GPGPU 2530 can beconfigured to operate as a compute cluster. In at least one embodiment,communication used by compute clusters 2536A-2536H for synchronizationand data exchange varies across embodiments. In at least one embodiment,multiple instances of GPGPU 2530 communicate over host interface 2532.In at least one embodiment, GPGPU 2530 includes an I/O hub 2539 thatcouples GPGPU 2530 with a GPU link 2540 that enables a direct connectionto other instances of GPGPU 2530. In at least one embodiment, GPU link2540 is coupled to a dedicated GPU-to-GPU bridge that enablescommunication and synchronization between multiple instances of GPGPU2530. In at least one embodiment GPU link 2540 couples with a high-speedinterconnect to transmit and receive data to other GPGPUs or parallelprocessors. In at least one embodiment, multiple instances of GPGPU 2530are located in separate data processing systems and communicate via anetwork device that is accessible via host interface 2532. In at leastone embodiment GPU link 2540 can be configured to enable a connection toa host processor in addition to or as an alternative to host interface2532.

In at least one embodiment, GPGPU 2530 can be configured to train neuralnetworks. In at least one embodiment, GPGPU 2530 can be used within aninferencing platform. In at least one embodiment, in which GPGPU 2530 isused for inferencing, GPGPU may include fewer compute clusters2536A-2536H relative to when GPGPU is used for training a neuralnetwork. In at least one embodiment, memory technology associated withmemory 2544A-2544B may differ between inferencing and trainingconfigurations, with higher bandwidth memory technologies devoted totraining configurations. In at least one embodiment, inferencingconfiguration of GPGPU 2530 can support inferencing specificinstructions. For example, in at least one embodiment, an inferencingconfiguration can provide support for one or more 8-bit integer dotproduct instructions, which may be used during inferencing operationsfor deployed neural networks.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 25B is used to implement techniques and/orfunctions described in connection with FIGS. 1-15B.

FIG. 26 is a block diagram illustrating a computing system 2600according to at least one embodiment. In at least one embodiment,computing system 2600 includes a processing subsystem 2601 having one ormore processor(s) 2602 and a system memory 2604 communicating via aninterconnection path that may include a memory hub 2605. In at least oneembodiment, memory hub 2605 may be a separate component within a chipsetcomponent or may be integrated within one or more processor(s) 2602. Inat least one embodiment, memory hub 2605 couples with an I/O subsystem2611 via a communication link 2606. In at least one embodiment, I/Osubsystem 2611 includes an I/O hub 2607 that can enable computing system2600 to receive input from one or more input device(s) 2608. In at leastone embodiment, I/O hub 2607 can enable a display controller, which maybe included in one or more processor(s) 2602, to provide outputs to oneor more display device(s) 2610A. In at least one embodiment, one or moredisplay device(s) 2610A coupled with I/O hub 2607 can include a local,internal, or embedded display device.

In at least one embodiment, processing subsystem 2601 includes one ormore parallel processor(s) 2612 coupled to memory hub 2605 via a bus orother communication link 2613. In at least one embodiment, communicationlink 2613 may be one of any number of standards based communication linktechnologies or protocols, such as, but not limited to PCI Express, ormay be a vendor specific communications interface or communicationsfabric. In at least one embodiment, one or more parallel processor(s)2612 form a computationally focused parallel or vector processing systemthat can include a large number of processing cores and/or processingclusters, such as a many integrated core (MIC) processor. In at leastone embodiment, one or more parallel processor(s) 2612 form a graphicsprocessing subsystem that can output pixels to one of one or moredisplay device(s) 2610A coupled via I/O Hub 2607. In at least oneembodiment, one or more parallel processor(s) 2612 can also include adisplay controller and display interface (not shown) to enable a directconnection to one or more display device(s) 2610B.

In at least one embodiment, a system storage unit 2614 can connect toI/O hub 2607 to provide a storage mechanism for computing system 2600.In at least one embodiment, an I/O switch 2616 can be used to provide aninterface mechanism to enable connections between I/O hub 2607 and othercomponents, such as a network adapter 2618 and/or wireless networkadapter 2619 that may be integrated into platform, and various otherdevices that can be added via one or more add-in device(s) 2620. In atleast one embodiment, network adapter 2618 can be an Ethernet adapter oranother wired network adapter. In at least one embodiment, wirelessnetwork adapter 2619 can include one or more of a Wi-Fi, Bluetooth, nearfield communication (NFC), or other network device that includes one ormore wireless radios.

In at least one embodiment, computing system 2600 can include othercomponents not explicitly shown, including USB or other portconnections, optical storage drives, video capture devices, and like,may also be connected to I/O hub 2607. In at least one embodiment,communication paths interconnecting various components in FIG. 26 may beimplemented using any suitable protocols, such as PCI (PeripheralComponent Interconnect) based protocols (e.g., PCI-Express), or otherbus or point-to-point communication interfaces and/or protocol(s), suchas NV-Link high-speed interconnect, or interconnect protocols.

In at least one embodiment, one or more parallel processor(s) 2612incorporate circuitry optimized for graphics and video processing,including, for example, video output circuitry, and constitutes agraphics processing unit (GPU). In at least one embodiment, one or moreparallel processor(s) 2612 incorporate circuitry optimized for generalpurpose processing. In at least embodiment, components of computingsystem 2600 may be integrated with one or more other system elements ona single integrated circuit. For example, in at least one embodiment,one or more parallel processor(s) 2612, memory hub 2605, processor(s)2602, and I/O hub 2607 can be integrated into a system on chip (SoC)integrated circuit. In at least one embodiment, components of computingsystem 2600 can be integrated into a single package to form a system inpackage (SIP) configuration. In at least one embodiment, at least aportion of components of computing system 2600 can be integrated into amulti-chip module (MCM), which can be interconnected with othermulti-chip modules into a modular computing system. In at least oneembodiment, at least one component shown or described with respect toFIG. 26 is used to implement techniques and/or functions described inconnection with FIGS. 1-15B.

Processors

FIG. 27A illustrates a parallel processor 2700 according to at least onembodiment. In at least one embodiment, various components of parallelprocessor 2700 may be implemented using one or more integrated circuitdevices, such as programmable processors, application specificintegrated circuits (ASICs), or field programmable gate arrays (FPGA).In at least one embodiment, illustrated parallel processor 2700 is avariant of one or more parallel processor(s) 2612 shown in FIG. 26according to an exemplary embodiment.

In at least one embodiment, parallel processor 2700 includes a parallelprocessing unit 2702. In at least one embodiment, parallel processingunit 2702 includes an I/O unit 2704 that enables communication withother devices, including other instances of parallel processing unit2702. In at least one embodiment, I/O unit 2704 may be directlyconnected to other devices. In at least one embodiment, I/O unit 2704connects with other devices via use of a hub or switch interface, suchas memory hub 2605. In at least one embodiment, connections betweenmemory hub 2605 and I/O unit 2704 form a communication link 2613. In atleast one embodiment, I/O unit 2704 connects with a host interface 2706and a memory crossbar 2716, where host interface 2706 receives commandsdirected to performing processing operations and memory crossbar 2716receives commands directed to performing memory operations.

In at least one embodiment, when host interface 2706 receives a commandbuffer via I/O unit 2704, host interface 2706 can direct work operationsto perform those commands to a front end 2708. In at least oneembodiment, front end 2708 couples with a scheduler 2710, which isconfigured to distribute commands or other work items to a processingcluster array 2712. In at least one embodiment, scheduler 2710 ensuresthat processing cluster array 2712 is properly configured and in a validstate before tasks are distributed to processing cluster array 2712 ofprocessing cluster array 2712. In at least one embodiment, scheduler2710 is implemented via firmware logic executing on a microcontroller.In at least one embodiment, microcontroller implemented scheduler 2710is configurable to perform complex scheduling and work distributionoperations at coarse and fine granularity, enabling rapid preemption andcontext switching of threads executing on processing array 2712. In atleast one embodiment, host software can prove workloads for schedulingon processing array 2712 via one of multiple graphics processingdoorbells. In at least one embodiment, workloads can then beautomatically distributed across processing array 2712 by scheduler 2710logic within a microcontroller including scheduler 2710.

In at least one embodiment, processing cluster array 2712 can include upto “N” processing clusters (e.g., cluster 2714A, cluster 2714B, throughcluster 2714N). In at least one embodiment, each cluster 2714A-2714N ofprocessing cluster array 2712 can execute a large number of concurrentthreads. In at least one embodiment, scheduler 2710 can allocate work toclusters 2714A-2714N of processing cluster array 2712 using variousscheduling and/or work distribution algorithms, which may vary dependingon workload arising for each type of program or computation. In at leastone embodiment, scheduling can be handled dynamically by scheduler 2710,or can be assisted in part by compiler logic during compilation ofprogram logic configured for execution by processing cluster array 2712.In at least one embodiment, different clusters 2714A-2714N of processingcluster array 2712 can be allocated for processing different types ofprograms or for performing different types of computations.

In at least one embodiment, processing cluster array 2712 can beconfigured to perform various types of parallel processing operations.In at least one embodiment, processing cluster array 2712 is configuredto perform general-purpose parallel compute operations. For example, inat least one embodiment, processing cluster array 2712 can include logicto execute processing tasks including filtering of video and/or audiodata, performing modeling operations, including physics operations, andperforming data transformations.

In at least one embodiment, processing cluster array 2712 is configuredto perform parallel graphics processing operations. In at least oneembodiment, processing cluster array 2712 can include additional logicto support execution of such graphics processing operations, including,but not limited to texture sampling logic to perform texture operations,as well as tessellation logic and other vertex processing logic. In atleast one embodiment, processing cluster array 2712 can be configured toexecute graphics processing related shader programs such as, but notlimited to vertex shaders, tessellation shaders, geometry shaders, andpixel shaders. In at least one embodiment, parallel processing unit 2702can transfer data from system memory via I/O unit 2704 for processing.In at least one embodiment, during processing, transferred data can bestored to on-chip memory (e.g., parallel processor memory 2722) duringprocessing, then written back to system memory.

In at least one embodiment, when parallel processing unit 2702 is usedto perform graphics processing, scheduler 2710 can be configured todivide a processing workload into approximately equal sized tasks, tobetter enable distribution of graphics processing operations to multipleclusters 2714A-2714N of processing cluster array 2712. In at least oneembodiment, portions of processing cluster array 2712 can be configuredto perform different types of processing. For example, in at least oneembodiment, a first portion may be configured to perform vertex shadingand topology generation, a second portion may be configured to performtessellation and geometry shading, and a third portion may be configuredto perform pixel shading or other screen space operations, to produce arendered image for display. In at least one embodiment, intermediatedata produced by one or more of clusters 2714A-2714N may be stored inbuffers to allow intermediate data to be transmitted between clusters2714A-2714N for further processing.

In at least one embodiment, processing cluster array 2712 can receiveprocessing tasks to be executed via scheduler 2710, which receivescommands defining processing tasks from front end 2708. In at least oneembodiment, processing tasks can include indices of data to beprocessed, e.g., surface (patch) data, primitive data, vertex data,and/or pixel data, as well as state parameters and commands defining howdata is to be processed (e.g., what program is to be executed). In atleast one embodiment, scheduler 2710 may be configured to fetch indicescorresponding to tasks or may receive indices from front end 2708. In atleast one embodiment, front end 2708 can be configured to ensureprocessing cluster array 2712 is configured to a valid state before aworkload specified by incoming command buffers (e.g., batch-buffers,push buffers, etc.) is initiated.

In at least one embodiment, each of one or more instances of parallelprocessing unit 2702 can couple with parallel processor memory 2722. Inat least one embodiment, parallel processor memory 2722 can be accessedvia memory crossbar 2716, which can receive memory requests fromprocessing cluster array 2712 as well as I/O unit 2704. In at least oneembodiment, memory crossbar 2716 can access parallel processor memory2722 via a memory interface 2718. In at least one embodiment, memoryinterface 2718 can include multiple partition units (e.g., partitionunit 2720A, partition unit 2720B, through partition unit 2720N) that caneach couple to a portion (e.g., memory unit) of parallel processormemory 2722. In at least one embodiment, a number of partition units2720A-2720N is configured to be equal to a number of memory units, suchthat a first partition unit 2720A has a corresponding first memory unit2724A, a second partition unit 2720B has a corresponding memory unit2724B, and an Nth partition unit 2720N has a corresponding Nth memoryunit 2724N. In at least one embodiment, a number of partition units2720A-2720N may not be equal to a number of memory devices.

In at least one embodiment, memory units 2724A-2724N can include varioustypes of memory devices, including dynamic random access memory (DRAM)or graphics random access memory, such as synchronous graphics randomaccess memory (SGRAM), including graphics double data rate (GDDR)memory. In at least one embodiment, memory units 2724A-2724N may alsoinclude 3D stacked memory, including but not limited to high bandwidthmemory (HBM). In at least one embodiment, render targets, such as framebuffers or texture maps may be stored across memory units 2724A-2724N,allowing partition units 2720A-2720N to write portions of each rendertarget in parallel to efficiently use available bandwidth of parallelprocessor memory 2722. In at least one embodiment, a local instance ofparallel processor memory 2722 may be excluded in favor of a unifiedmemory design that utilizes system memory in conjunction with localcache memory.

In at least one embodiment, any one of clusters 2714A-2714N ofprocessing cluster array 2712 can process data that will be written toany of memory units 2724A-2724N within parallel processor memory 2722.In at least one embodiment, memory crossbar 2716 can be configured totransfer an output of each cluster 2714A-2714N to any partition unit2720A-2720N or to another cluster 2714A-2714N, which can performadditional processing operations on an output. In at least oneembodiment, each cluster 2714A-2714N can communicate with memoryinterface 2718 through memory crossbar 2716 to read from or write tovarious external memory devices. In at least one embodiment, memorycrossbar 2716 has a connection to memory interface 2718 to communicatewith I/O unit 2704, as well as a connection to a local instance ofparallel processor memory 2722, enabling processing units withindifferent processing clusters 2714A-2714N to communicate with systemmemory or other memory that is not local to parallel processing unit2702. In at least one embodiment, memory crossbar 2716 can use virtualchannels to separate traffic streams between clusters 2714A-2714N andpartition units 2720A-2720N.

In at least one embodiment, multiple instances of parallel processingunit 2702 can be provided on a single add-in card, or multiple add-incards can be interconnected. In at least one embodiment, differentinstances of parallel processing unit 2702 can be configured tointer-operate even if different instances have different numbers ofprocessing cores, different amounts of local parallel processor memory,and/or other configuration differences. For example, in at least oneembodiment, some instances of parallel processing unit 2702 can includehigher precision floating point units relative to other instances. In atleast one embodiment, systems incorporating one or more instances ofparallel processing unit 2702 or parallel processor 2700 can beimplemented in a variety of configurations and form factors, includingbut not limited to desktop, laptop, or handheld personal computers,servers, workstations, game consoles, and/or embedded systems.

FIG. 27B is a block diagram of a partition unit 2720 according to atleast one embodiment. In at least one embodiment, partition unit 2720 isan instance of one of partition units 2720A-2720N of FIG. 27A. In atleast one embodiment, partition unit 2720 includes an L2 cache 2721, aframe buffer interface 2725, and a ROP 2726 (raster operations unit). L2cache 2721 is a read/write cache that is configured to perform load andstore operations received from memory crossbar 2716 and ROP 2726. In atleast one embodiment, read misses and urgent write-back requests areoutput by L2 cache 2721 to frame buffer interface 2725 for processing.In at least one embodiment, updates can also be sent to a frame buffervia frame buffer interface 2725 for processing. In at least oneembodiment, frame buffer interface 2725 interfaces with one of memoryunits in parallel processor memory, such as memory units 2724A-2724N ofFIG. 27 (e.g., within parallel processor memory 2722).

In at least one embodiment, ROP 2726 is a processing unit that performsraster operations such as stencil, z test, blending, and like. In atleast one embodiment, ROP 2726 then outputs processed graphics data thatis stored in graphics memory. In at least one embodiment, ROP 2726includes compression logic to compress depth or color data that iswritten to memory and decompress depth or color data that is read frommemory. In at least one embodiment, compression logic can be losslesscompression logic that makes use of one or more of multiple compressionalgorithms. In at least one embodiment, type of compression that isperformed by ROP 2726 can vary based on statistical characteristics ofdata to be compressed. For example, in at least one embodiment, deltacolor compression is performed on depth and color data on a per-tilebasis.

In In at least one embodiment, ROP 2726 is included within eachprocessing cluster (e.g., cluster 2714A-2714N of FIG. 27 ) instead ofwithin partition unit 2720. In at least one embodiment, read and writerequests for pixel data are transmitted over memory crossbar 2716instead of pixel fragment data. In at least one embodiment, processedgraphics data may be displayed on a display device, such as one of oneor more display device(s) 2610 of FIG. 26 , routed for furtherprocessing by processor(s) 2602, or routed for further processing by oneof processing entities within parallel processor 2700 of FIG. 27A.

FIG. 27C is a block diagram of a processing cluster 2714 within aparallel processing unit according to at least one embodiment. In atleast one embodiment, a processing cluster is an instance of one ofprocessing clusters 2714A-2714N of FIG. 27 . In at least one embodiment,processing cluster 2714 can be configured to execute many threads inparallel, where term “thread” refers to an instance of a particularprogram executing on a particular set of input data. In at least oneembodiment, single-instruction, multiple-data (SIMD) instruction issuetechniques are used to support parallel execution of a large number ofthreads without providing multiple independent instruction units. In atleast one embodiment, single-instruction, multiple-thread (SIMT)techniques are used to support parallel execution of a large number ofgenerally synchronized threads, using a common instruction unitconfigured to issue instructions to a set of processing engines withineach one of processing clusters.

In at least one embodiment, operation of processing cluster 2714 can becontrolled via a pipeline manager 2732 that distributes processing tasksto SIMT parallel processors. In at least one embodiment, pipelinemanager 2732 receives instructions from scheduler 2710 of FIG. 27 andmanages execution of those instructions via a graphics multiprocessor2734 and/or a texture unit 2736. In at least one embodiment, graphicsmultiprocessor 2734 is an exemplary instance of a SIMT parallelprocessor. However, in at least one embodiment, various types of SIMTparallel processors of differing architectures may be included withinprocessing cluster 2714. In at least one embodiment, one or moreinstances of graphics multiprocessor 2734 can be included within aprocessing cluster 2714. In at least one embodiment, graphicsmultiprocessor 2734 can process data and a data crossbar 2740 can beused to distribute processed data to one of multiple possibledestinations, including other shader units. In at least one embodiment,pipeline manager 2732 can facilitate distribution of processed data byspecifying destinations for processed data to be distributed via datacrossbar 2740.

In at least one embodiment, each graphics multiprocessor 2734 withinprocessing cluster 2714 can include an identical set of functionalexecution logic (e.g., arithmetic logic units, load-store units, etc.).In at least one embodiment, functional execution logic can be configuredin a pipelined manner in which new instructions can be issued beforeprevious instructions are complete. In at least one embodiment,functional execution logic supports a variety of operations includinginteger and floating point arithmetic, comparison operations, Booleanoperations, bit-shifting, and computation of various algebraicfunctions. In at least one embodiment, same functional-unit hardware canbe leveraged to perform different operations and any combination offunctional units may be present.

In at least one embodiment, instructions transmitted to processingcluster 2714 constitute a thread. In at least one embodiment, a set ofthreads executing across a set of parallel processing engines is athread group. In at least one embodiment, thread group executes aprogram on different input data. In at least one embodiment, each threadwithin a thread group can be assigned to a different processing enginewithin a graphics multiprocessor 2734. In at least one embodiment, athread group may include fewer threads than a number of processingengines within graphics multiprocessor 2734. In at least one embodiment,when a thread group includes fewer threads than a number of processingengines, one or more of processing engines may be idle during cycles inwhich that thread group is being processed. In at least one embodiment,a thread group may also include more threads than a number of processingengines within graphics multiprocessor 2734. In at least one embodiment,when a thread group includes more threads than number of processingengines within graphics multiprocessor 2734, processing can be performedover consecutive clock cycles. In at least one embodiment, multiplethread groups can be executed concurrently on a graphics multiprocessor2734.

In at least one embodiment, graphics multiprocessor 2734 includes aninternal cache memory to perform load and store operations. In at leastone embodiment, graphics multiprocessor 2734 can forego an internalcache and use a cache memory (e.g., L1 cache 2748) within processingcluster 2714. In at least one embodiment, each graphics multiprocessor2734 also has access to L2 caches within partition units (e.g.,partition units 2720A-2720N of FIG. 27 ) that are shared among allprocessing clusters 2714 and may be used to transfer data betweenthreads. In at least one embodiment, graphics multiprocessor 2734 mayalso access off-chip global memory, which can include one or more oflocal parallel processor memory and/or system memory. In at least oneembodiment, any memory external to parallel processing unit 2702 may beused as global memory. In at least one embodiment, processing cluster2714 includes multiple instances of graphics multiprocessor 2734 canshare common instructions and data, which may be stored in L1 cache2748.

In at least one embodiment, each processing cluster 2714 may include anMMU 2745 (memory management unit) that is configured to map virtualaddresses into physical addresses. In at least one embodiment, one ormore instances of MMU 2745 may reside within memory interface 2718 ofFIG. 27 . In at least one embodiment, MMU 2745 includes a set of pagetable entries (PTEs) used to map a virtual address to a physical addressof a tile and optionally a cache line index. In at least one embodiment,MMU 2745 may include address translation lookaside buffers (TLB) orcaches that may reside within graphics multiprocessor 2734 or L1 cacheor processing cluster 2714. In at least one embodiment, physical addressis processed to distribute surface data access locality to allowefficient request interleaving among partition units. In at least oneembodiment, cache line index may be used to determine whether a requestfor a cache line is a hit or miss.

In at least one embodiment, a processing cluster 2714 may be configuredsuch that each graphics multiprocessor 2734 is coupled to a texture unit2736 for performing texture mapping operations, e.g., determiningtexture sample positions, reading texture data, and filtering texturedata. In at least one embodiment, texture data is read from an internaltexture L1 cache (not shown) or from an L1 cache within graphicsmultiprocessor 2734 and is fetched from an L2 cache, local parallelprocessor memory, or system memory, as needed. In at least oneembodiment, each graphics multiprocessor 2734 outputs processed tasks todata crossbar 2740 to provide processed task to another processingcluster 2714 for further processing or to store processed task in an L2cache, local parallel processor memory, or system memory via memorycrossbar 2716. In at least one embodiment, preROP 2742 (pre-rasteroperations unit) is configured to receive data from graphicsmultiprocessor 2734, direct data to ROP units, which may be located withpartition units as described herein (e.g., partition units 2720A-2720Nof FIG. 27 ). In at least one embodiment, PreROP 2742 unit can performoptimizations for color blending, organize pixel color data, and performaddress translations. In at least one embodiment, at least one componentshown or described with respect to FIG. 27A-27C is used to implementtechniques and/or functions described in connection with FIGS. 1-15B.

FIG. 27D shows a graphics multiprocessor 2734 according to at least oneembodiment. In at least one embodiment, graphics multiprocessor 2734couples with pipeline manager 2732 of processing cluster 2714. In atleast one embodiment, graphics multiprocessor 2734 has an executionpipeline including but not limited to an instruction cache 2752, aninstruction unit 2754, an address mapping unit 2756, a register file2758, one or more general purpose graphics processing unit (GPGPU) cores2762, and one or more load/store units 2766. GPGPU cores 2762 andload/store units 2766 are coupled with cache memory 2772 and sharedmemory 2770 via a memory and cache interconnect 2768.

In at least one embodiment, instruction cache 2752 receives a stream ofinstructions to execute from pipeline manager 2732. In at least oneembodiment, instructions are cached in instruction cache 2752 anddispatched for execution by instruction unit 2754. In at least oneembodiment, instruction unit 2754 can dispatch instructions as threadgroups (e.g., warps), with each thread of thread group assigned to adifferent execution unit within GPGPU core 2762. In at least oneembodiment, an instruction can access any of a local, shared, or globaladdress space by specifying an address within a unified address space.In at least one embodiment, address mapping unit 2756 can be used totranslate addresses in a unified address space into a distinct memoryaddress that can be accessed by load/store units 2766.

In at least one embodiment, register file 2758 provides a set ofregisters for functional units of graphics multiprocessor 2734. In atleast one embodiment, register file 2758 provides temporary storage foroperands connected to data paths of functional units (e.g., GPGPU cores2762, load/store units 2766) of graphics multiprocessor 2734. In atleast one embodiment, register file 2758 is divided between each offunctional units such that each functional unit is allocated a dedicatedportion of register file 2758. In at least one embodiment, register file2758 is divided between different warps being executed by graphicsmultiprocessor 2734.

In at least one embodiment, GPGPU cores 2762 can each include floatingpoint units (FPUs) and/or integer arithmetic logic units (ALUs) that areused to execute instructions of graphics multiprocessor 2734. GPGPUcores 2762 can be similar in architecture or can differ in architecture.In at least one embodiment, a first portion of GPGPU cores 2762 includea single precision FPU and an integer ALU while a second portion ofGPGPU cores include a double precision FPU. In at least one embodiment,FPUs can implement IEEE 754-2008 standard for floating point arithmeticor enable variable precision floating point arithmetic. In at least oneembodiment, graphics multiprocessor 2734 can additionally include one ormore fixed function or special function units to perform specificfunctions such as copy rectangle or pixel blending operations. In atleast one embodiment one or more of GPGPU cores can also include fixedor special function logic.

In at least one embodiment, GPGPU cores 2762 include SIMD logic capableof performing a single instruction on multiple sets of data. In at leastone embodiment GPGPU cores 2762 can physically execute SIMD4, SIMD8, andSIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32instructions. In at least one embodiment, SIMD instructions for GPGPUcores can be generated at compile time by a shader compiler orautomatically generated when executing programs written and compiled forsingle program multiple data (SPMD) or SIMT architectures. In at leastone embodiment, multiple threads of a program configured for an SIMTexecution model can executed via a single SIMD instruction. For example,in at least one embodiment, eight SIMT threads that perform same orsimilar operations can be executed in parallel via a single SIMD8 logicunit.

In at least one embodiment, memory and cache interconnect 2768 is aninterconnect network that connects each functional unit of graphicsmultiprocessor 2734 to register file 2758 and to shared memory 2770. Inat least one embodiment, memory and cache interconnect 2768 is acrossbar interconnect that allows load/store unit 2766 to implement loadand store operations between shared memory 2770 and register file 2758.In at least one embodiment, register file 2758 can operate at a samefrequency as GPGPU cores 2762, thus data transfer between GPGPU cores2762 and register file 2758 is very low latency. In at least oneembodiment, shared memory 2770 can be used to enable communicationbetween threads that execute on functional units within graphicsmultiprocessor 2734. In at least one embodiment, cache memory 2772 canbe used as a data cache for example, to cache texture data communicatedbetween functional units and texture unit 2736. In at least oneembodiment, shared memory 2770 can also be used as a program managedcached. In at least one embodiment, threads executing on GPGPU cores2762 can programmatically store data within shared memory in addition toautomatically cached data that is stored within cache memory 2772.

In at least one embodiment, a parallel processor or GPGPU as describedherein is communicatively coupled to host/processor cores to accelerategraphics operations, machine-learning operations, pattern analysisoperations, and various general purpose GPU (GPGPU) functions. In atleast one embodiment, GPU may be communicatively coupled to hostprocessor/cores over a bus or other interconnect (e.g., a high-speedinterconnect such as PCIe or NVLink). In at least one embodiment, GPUmay be integrated on same package or chip as cores and communicativelycoupled to cores over an internal processor bus/interconnect (i.e.,internal to package or chip). In at least one embodiment, regardless ofmanner in which GPU is connected, processor cores may allocate work toGPU in form of sequences of commands/instructions contained in a workdescriptor. In at least one embodiment, GPU then uses dedicatedcircuitry/logic for efficiently processing these commands/instructions.In at least one embodiment, at least one component shown or describedwith respect to FIG. 27D is used to implement techniques and/orfunctions described in connection with FIGS. 1-15B.

FIG. 28 illustrates a multi-GPU computing system 2800, according to atleast one embodiment. In at least one embodiment, multi-GPU computingsystem 2800 can include a processor 2802 coupled to multiple generalpurpose graphics processing units (GPGPUs) 2806A-D via a host interfaceswitch 2804. In at least one embodiment, host interface switch 2804 is aPCI express switch device that couples processor 2802 to a PCI expressbus over which processor 2802 can communicate with GPGPUs 2806A-D.GPGPUs 2806A-D can interconnect via a set of high-speed point to pointGPU to GPU links 2816. In at least one embodiment, GPU to GPU links 2816connect to each of GPGPUs 2806A-D via a dedicated GPU link. In at leastone embodiment, P2P GPU links 2816 enable direct communication betweeneach of GPGPUs 2806A-D without requiring communication over hostinterface bus 2804 to which processor 2802 is connected. In at least oneembodiment, with GPU-to-GPU traffic directed to P2P GPU links 2816, hostinterface bus 2804 remains available for system memory access or tocommunicate with other instances of multi-GPU computing system 2800, forexample, via one or more network devices. While in at least oneembodiment GPGPUs 2806A-D connect to processor 2802 via host interfaceswitch 2804, in at least one embodiment processor 2802 includes directsupport for P2P GPU links 2816 and can connect directly to GPGPUs2806A-D. In at least one embodiment, at least one component shown ordescribed with respect to FIG. 28 is used to implement techniques and/orfunctions described in connection with FIGS. 1-15B.

FIG. 29 is a block diagram of a graphics processor 2900, according to atleast one embodiment. In at least one embodiment, graphics processor2900 includes a ring interconnect 2902, a pipeline front-end 2904, amedia engine 2937, and graphics cores 2980A-2980N. In at least oneembodiment, ring interconnect 2902 couples graphics processor 2900 toother processing units, including other graphics processors or one ormore general-purpose processor cores. In at least one embodiment,graphics processor 2900 is one of many processors integrated within amulti-core processing system.

In at least one embodiment, graphics processor 2900 receives batches ofcommands via ring interconnect 2902. In at least one embodiment,incoming commands are interpreted by a command streamer 2903 in pipelinefront-end 2904. In at least one embodiment, graphics processor 2900includes scalable execution logic to perform 3D geometry processing andmedia processing via graphics core(s) 2980A-2980N. In at least oneembodiment, for 3D geometry processing commands, command streamer 2903supplies commands to geometry pipeline 2936. In at least one embodiment,for at least some media processing commands, command streamer 2903supplies commands to a video front end 2934, which couples with a mediaengine 2937. In at least one embodiment, media engine 2937 includes aVideo Quality Engine (VQE) 2930 for video and image post-processing anda multi-format encode/decode (MFX) 2933 engine to providehardware-accelerated media data encode and decode. In at least oneembodiment, geometry pipeline 2936 and media engine 2937 each generateexecution threads for thread execution resources provided by at leastone graphics core 2980A.

In at least one embodiment, graphics processor 2900 includes scalablethread execution resources featuring modular cores 2980A-2980N(sometimes referred to as core slices), each having multiple sub-cores2950A-550N, 2960A-2960N (sometimes referred to as core sub-slices). Inat least one embodiment, graphics processor 2900 can have any number ofgraphics cores 2980A through 2980N. In at least one embodiment, graphicsprocessor 2900 includes a graphics core 2980A having at least a firstsub-core 2950A and a second sub-core 2960A. In at least one embodiment,graphics processor 2900 is a low power processor with a single sub-core(e.g., 2950A). In at least one embodiment, graphics processor 2900includes multiple graphics cores 2980A-2980N, each including a set offirst sub-cores 2950A-2950N and a set of second sub-cores 2960A-2960N.In at least one embodiment, each sub-core in first sub-cores 2950A-2950Nincludes at least a first set of execution units 2952A-2952N andmedia/texture samplers 2954A-2954N. In at least one embodiment, eachsub-core in second sub-cores 2960A-2960N includes at least a second setof execution units 2962A-2962N and samplers 2964A-2964N. In at least oneembodiment, each sub-core 2950A-2950N, 2960A-2960N shares a set ofshared resources 2970A-2970N. In at least one embodiment, sharedresources include shared cache memory and pixel operation logic. In atleast one embodiment, at least one component shown or described withrespect to FIG. 29 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-15B.

FIG. 30 is a block diagram illustrating micro-architecture for aprocessor 3000 that may include logic circuits to perform instructions,according to at least one embodiment. In at least one embodiment,processor 3000 may perform instructions, including x86 instructions, ARMinstructions, specialized instructions for application-specificintegrated circuits (ASICs), etc. In at least one embodiment, processor3010 may include registers to store packed data, such as 64-bit wideMMX™ registers in microprocessors enabled with MMX technology from IntelCorporation of Santa Clara, Calif In at least one embodiment, MMXregisters, available in both integer and floating point forms, mayoperate with packed data elements that accompany single instruction,multiple data (“SIMD”) and streaming SIMD extensions (“SSE”)instructions. In at least one embodiment, 128-bit wide XMM registersrelating to SSE2, SSE3, SSE4, AVX, or beyond (referred to generically as“SSEx”) technology may hold such packed data operands. In at least oneembodiment, processors 3010 may perform instructions to acceleratemachine learning or deep learning algorithms, training, or inferencing.

In at least one embodiment, processor 3000 includes an in-order frontend (“front end”) 3001 to fetch instructions to be executed and prepareinstructions to be used later in processor pipeline. In at least oneembodiment, front end 3001 may include several units. In at least oneembodiment, an instruction prefetcher 3026 fetches instructions frommemory and feeds instructions to an instruction decoder 3028 which inturn decodes or interprets instructions. For example, in at least oneembodiment, instruction decoder 3028 decodes a received instruction intoone or more operations called “micro-instructions” or “micro-operations”(also called “micro ops” or “uops”) that machine may execute. In atleast one embodiment, instruction decoder 3028 parses instruction intoan opcode and corresponding data and control fields that may be used bymicro-architecture to perform operations in accordance with at least oneembodiment. In at least one embodiment, a trace cache 3030 may assembledecoded uops into program ordered sequences or traces in a uop queue3034 for execution. In at least one embodiment, when trace cache 3030encounters a complex instruction, a microcode ROM 3032 provides uopsneeded to complete operation.

In at least one embodiment, some instructions may be converted into asingle micro-op, whereas others need several micro-ops to complete fulloperation. In at least one embodiment, if more than four micro-ops areneeded to complete an instruction, instruction decoder 3028 may accessmicrocode ROM 3032 to perform instruction. In at least one embodiment,an instruction may be decoded into a small number of micro-ops forprocessing at instruction decoder 3028. In at least one embodiment, aninstruction may be stored within microcode ROM 3032 should a number ofmicro-ops be needed to accomplish operation. In at least one embodiment,trace cache 3030 refers to an entry point programmable logic array(“PLA”) to determine a correct micro-instruction pointer for readingmicrocode sequences to complete one or more instructions from microcodeROM 3032 in accordance with at least one embodiment. In at least oneembodiment, after microcode ROM 3032 finishes sequencing micro-ops foran instruction, front end 3001 of machine may resume fetching micro-opsfrom trace cache 3030.

In at least one embodiment, out-of-order execution engine (“out of orderengine”) 3003 may prepare instructions for execution. In at least oneembodiment, out-of-order execution logic has a number of buffers tosmooth out and re-order flow of instructions to optimize performance asthey go down pipeline and get scheduled for execution. out-of-orderexecution engine 3003 includes, without limitation, anallocator/register renamer 3040, a memory uop queue 3042, aninteger/floating point uop queue 3044, a memory scheduler 3046, a fastscheduler 3002, a slow/general floating point scheduler (“slow/generalFP scheduler”) 3004, and a simple floating point scheduler (“simple FPscheduler”) 3006. In at least one embodiment, fast schedule 3002,slow/general floating point scheduler 3004, and simple floating pointscheduler 3006 are also collectively referred to herein as “uopschedulers 3002, 3004, 3006.” In at least one embodiment,allocator/register renamer 3040 allocates machine buffers and resourcesthat each uop needs in order to execute. In at least one embodiment,allocator/register renamer 3040 renames logic registers onto entries ina register file. In at least one embodiment, allocator/register renamer3040 also allocates an entry for each uop in one of two uop queues,memory uop queue 3042 for memory operations and integer/floating pointuop queue 3044 for non-memory operations, in front of memory scheduler3046 and uop schedulers 3002, 3004, 3006. In at least one embodiment,uop schedulers 3002, 3004, 3006, determine when a uop is ready toexecute based on readiness of their dependent input register operandsources and availability of execution resources uops need to completetheir operation. In at least one embodiment, fast scheduler 3002 of atleast one embodiment may schedule on each half of main clock cycle whileslow/general floating point scheduler 3004 and simple floating pointscheduler 3006 may schedule once per main processor clock cycle. In atleast one embodiment, uop schedulers 3002, 3004, 3006 arbitrate fordispatch ports to schedule uops for execution.

In at least one embodiment, execution block b 11 includes, withoutlimitation, an integer register file/bypass network 3008, a floatingpoint register file/bypass network (“FP register file/bypass network”)3010, address generation units (“AGUs”) 3012 and 3014, fast ArithmeticLogic Units (ALUs) (“fast ALUs”) 3016 and 3018, a slow Arithmetic LogicUnit (“slow ALU”) 3020, a floating point ALU (“FP”) 3022, and a floatingpoint move unit (“FP move”) 3024. In at least one embodiment, integerregister file/bypass network 3008 and floating point registerfile/bypass network 3010 are also referred to herein as “register files3008, 3010.” In at least one embodiment, AGUSs 3012 and 3014, fast ALUs3016 and 3018, slow ALU 3020, floating point ALU 3022, and floatingpoint move unit 3024 are also referred to herein as “execution units3012, 3014, 3016, 3018, 3020, 3022, and 3024.” In at least oneembodiment, execution block b 11 may include, without limitation, anynumber (including zero) and type of register files, bypass networks,address generation units, and execution units, in any combination.

In at least one embodiment, register files 3008, 3010 may be arrangedbetween uop schedulers 3002, 3004, 3006, and execution units 3012, 3014,3016, 3018, 3020, 3022, and 3024. In at least one embodiment, integerregister file/bypass network 3008 performs integer operations. In atleast one embodiment, floating point register file/bypass network 3010performs floating point operations. In at least one embodiment, each ofregister files 3008, 3010 may include, without limitation, a bypassnetwork that may bypass or forward just completed results that have notyet been written into register file to new dependent uops. In at leastone embodiment, register files 3008, 3010 may communicate data with eachother. In at least one embodiment, integer register file/bypass network3008 may include, without limitation, two separate register files, oneregister file for low-order thirty-two bits of data and a secondregister file for high order thirty-two bits of data. In at least oneembodiment, floating point register file/bypass network 3010 mayinclude, without limitation, 128-bit wide entries because floating pointinstructions typically have operands from 64 to 128 bits in width.

In at least one embodiment, execution units 3012, 3014, 3016, 3018,3020, 3022, 3024 may execute instructions. In at least one embodiment,register files 3008, 3010 store integer and floating point data operandvalues that micro-instructions need to execute. In at least oneembodiment, processor 3000 may include, without limitation, any numberand combination of execution units 3012, 3014, 3016, 3018, 3020, 3022,3024. In at least one embodiment, floating point ALU 3022 and floatingpoint move unit 3024, may execute floating point, MMX, SIMD, AVX andSSE, or other operations, including specialized machine learninginstructions. In at least one embodiment, floating point ALU 3022 mayinclude, without limitation, a 64-bit by 64-bit floating point dividerto execute divide, square root, and remainder micro ops. In at least oneembodiment, instructions involving a floating point value may be handledwith floating point hardware. In at least one embodiment, ALU operationsmay be passed to fast ALUs 3016, 3018. In at least one embodiment, fastALUS 3016, 3018 may execute fast operations with an effective latency ofhalf a clock cycle. In at least one embodiment, most complex integeroperations go to slow ALU 3020 as slow ALU 3020 may include, withoutlimitation, integer execution hardware for long-latency type ofoperations, such as a multiplier, shifts, flag logic, and branchprocessing. In at least one embodiment, memory load/store operations maybe executed by AGUS 3012, 3014. In at least one embodiment, fast ALU3016, fast ALU 3018, and slow ALU 3020 may perform integer operations on64-bit data operands. In at least one embodiment, fast ALU 3016, fastALU 3018, and slow ALU 3020 may be implemented to support a variety ofdata bit sizes including sixteen, thirty-two, 128, 256, etc. In at leastone embodiment, floating point ALU 3022 and floating point move unit3024 may be implemented to support a range of operands having bits ofvarious widths. In at least one embodiment, floating point ALU 3022 andfloating point move unit 3024 may operate on 128-bit wide packed dataoperands in conjunction with SIMD and multimedia instructions.

In at least one embodiment, uop schedulers 3002, 3004, 3006, dispatchdependent operations before parent load has finished executing. In atleast one embodiment, as uops may be speculatively scheduled andexecuted in processor 3000, processor 3000 may also include logic tohandle memory misses. In at least one embodiment, if a data load missesin data cache, there may be dependent operations in flight in pipelinethat have left scheduler with temporarily incorrect data. In at leastone embodiment, a replay mechanism tracks and re-executes instructionsthat use incorrect data. In at least one embodiment, dependentoperations might need to be replayed and independent ones may be allowedto complete. In at least one embodiment, schedulers and replay mechanismof at least one embodiment of a processor may also be designed to catchinstruction sequences for text string comparison operations.

In at least one embodiment, term “registers” may refer to on-boardprocessor storage locations that may be used as part of instructions toidentify operands. In at least one embodiment, registers may be thosethat may be usable from outside of processor (from a programmer'sperspective). In at least one embodiment, registers might not be limitedto a particular type of circuit. Rather, in at least one embodiment, aregister may store data, provide data, and perform functions describedherein. In at least one embodiment, registers described herein may beimplemented by circuitry within a processor using any number ofdifferent techniques, such as dedicated physical registers, dynamicallyallocated physical registers using register renaming, combinations ofdedicated and dynamically allocated physical registers, etc. In at leastone embodiment, integer registers store 32-bit integer data. A registerfile of at least one embodiment also contains eight multimedia SIMDregisters for packed data. In at least one embodiment, at least onecomponent shown or described with respect to FIG. 30 is used toimplement techniques and/or functions described in connection with FIGS.1-15B.

FIG. 31 is a block diagram of a processing system, according to at leastone embodiment. In at least one embodiment, system 3100 includes one ormore processors 3102 and one or more graphics processors 3108, and maybe a single processor desktop system, a multiprocessor workstationsystem, or a server system having a large number of processors 3102 orprocessor cores 3107. In at least one embodiment, system 3100 is aprocessing platform incorporated within a system-on-a-chip (SoC)integrated circuit for use in mobile, handheld, or embedded devices.

In at least one embodiment, system 3100 can include, or be incorporatedwithin a server-based gaming platform, a game console, including a gameand media console, a mobile gaming console, a handheld game console, oran online game console. In at least one embodiment, system 3100 is amobile phone, smart phone, tablet computing device or mobile Internetdevice. In at least one embodiment, processing system 3100 can alsoinclude, couple with, or be integrated within a wearable device, such asa smart watch wearable device, smart eyewear device, augmented realitydevice, or virtual reality device. In at least one embodiment,processing system 3100 is a television or set top box device having oneor more processors 3102 and a graphical interface generated by one ormore graphics processors 3108.

In at least one embodiment, one or more processors 3102 each include oneor more processor cores 3107 to process instructions which, whenexecuted, perform operations for system and user software. In at leastone embodiment, each of one or more processor cores 3107 is configuredto process a specific instruction set 3109. In at least one embodiment,instruction set 3109 may facilitate Complex Instruction Set Computing(CISC), Reduced Instruction Set Computing (RISC), or computing via aVery Long Instruction Word (VLIW). In at least one embodiment, processorcores 3107 may each process a different instruction set 3109, which mayinclude instructions to facilitate emulation of other instruction sets.In at least one embodiment, processor core 3107 may also include otherprocessing devices, such a Digital Signal Processor (DSP).

In at least one embodiment, processor 3102 includes cache memory 3104.In at least one embodiment, processor 3102 can have a single internalcache or multiple levels of internal cache. In at least one embodiment,cache memory is shared among various components of processor 3102. In atleast one embodiment, processor 3102 also uses an external cache (e.g.,a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which maybe shared among processor cores 3107 using known cache coherencytechniques. In at least one embodiment, register file 3106 isadditionally included in processor 3102 which may include differenttypes of registers for storing different types of data (e.g., integerregisters, floating point registers, status registers, and aninstruction pointer register). In at least one embodiment, register file3106 may include general-purpose registers or other registers.

In at least one embodiment, one or more processor(s) 3102 are coupledwith one or more interface bus (es) 3110 to transmit communicationsignals such as address, data, or control signals between processor 3102and other components in system 3100. In at least one embodimentinterface bus 3110, in one embodiment, can be a processor bus, such as aversion of a Direct Media Interface (DMI) bus. In at least oneembodiment, interface 3110 is not limited to a DMI bus, and may includeone or more Peripheral Component Interconnect buses (e.g., PCI, PCIExpress), memory busses, or other types of interface busses. In at leastone embodiment processor(s) 3102 include an integrated memory controller3116 and a platform controller hub 3130. In at least one embodiment,memory controller 3116 facilitates communication between a memory deviceand other components of system 3100, while platform controller hub (PCH)3130 provides connections to I/O devices via a local I/O bus.

In at least one embodiment, memory device 3120 can be a dynamic randomaccess memory (DRAM) device, a static random access memory (SRAM)device, flash memory device, phase-change memory device, or some othermemory device having suitable performance to serve as process memory. Inat least one embodiment memory device 3120 can operate as system memoryfor system 3100, to store data 3122 and instructions 3121 for use whenone or more processors 3102 executes an application or process. In atleast one embodiment, memory controller 3116 also couples with anoptional external graphics processor 3112, which may communicate withone or more graphics processors 3108 in processors 3102 to performgraphics and media operations. In at least one embodiment, a displaydevice 3111 can connect to processor(s) 3102. In at least one embodimentdisplay device 3111 can include one or more of an internal displaydevice, as in a mobile electronic device or a laptop device or anexternal display device attached via a display interface (e.g.,DisplayPort, etc.). In at least one embodiment, display device 3111 caninclude a head mounted display (HMD) such as a stereoscopic displaydevice for use in virtual reality (VR) applications or augmented reality(AR) applications.

In at least one embodiment, platform controller hub 3130 enablesperipherals to connect to memory device 3120 and processor 3102 via ahigh-speed I/O bus. In at least one embodiment, I/O peripherals include,but are not limited to, an audio controller 3146, a network controller3134, a firmware interface 3128, a wireless transceiver 3126, touchsensors 3125, a data storage device 3124 (e.g., hard disk drive, flashmemory, etc.). In at least one embodiment, data storage device 3124 canconnect via a storage interface (e.g., SATA) or via a peripheral bus,such as a Peripheral Component Interconnect bus (e.g., PCI, PCIExpress). In at least one embodiment, touch sensors 3125 can includetouch screen sensors, pressure sensors, or fingerprint sensors. In atleast one embodiment, wireless transceiver 3126 can be a Wi-Fitransceiver, a Bluetooth transceiver, or a mobile network transceiversuch as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at leastone embodiment, firmware interface 3128 enables communication withsystem firmware, and can be, for example, a unified extensible firmwareinterface (UEFI). In at least one embodiment, network controller 3134can enable a network connection to a wired network. In at least oneembodiment, a high-performance network controller (not shown) coupleswith interface bus 3110. In at least one embodiment, audio controller3146 is a multi-channel high definition audio controller. In at leastone embodiment, system 3100 includes an optional legacy I/O controller3140 for coupling legacy (e.g., Personal System 2 (PS/2)) devices tosystem. In at least one embodiment, platform controller hub 3130 canalso connect to one or more Universal Serial Bus (USB) controllers 3142connect input devices, such as keyboard and mouse 3143 combinations, acamera 3144, or other USB input devices.

In at least one embodiment, an instance of memory controller 3116 andplatform controller hub 3130 may be integrated into a discreet externalgraphics processor, such as external graphics processor 3112. In atleast one embodiment, platform controller hub 3130 and/or memorycontroller 3116 may be external to one or more processor(s) 3102. Forexample, in at least one embodiment, system 3100 can include an externalmemory controller 3116 and platform controller hub 3130, which may beconfigured as a memory controller hub and peripheral controller hubwithin a system chipset that is in communication with processor(s) 3102.In at least one embodiment, at least one component shown or describedwith respect to FIG. 31 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-15B.

FIG. 32 is a block diagram of a processor 3200 having one or moreprocessor cores 3202A-3202N, an integrated memory controller 3214, andan integrated graphics processor 3208, according to at least oneembodiment. In at least one embodiment, processor 3200 can includeadditional cores up to and including additional core 3202N representedby dashed lined boxes. In at least one embodiment, each of processorcores 3202A-3202N includes one or more internal cache units 3204A-3204N.In at least one embodiment, each processor core also has access to oneor more shared cached units 3206.

In at least one embodiment, internal cache units 3204A-3204N and sharedcache units 3206 represent a cache memory hierarchy within processor3200. In at least one embodiment, cache memory units 3204A-3204N mayinclude at least one level of instruction and data cache within eachprocessor core and one or more levels of shared mid-level cache, such asa Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache,where a highest level of cache before external memory is classified asan LLC. In at least one embodiment, cache coherency logic maintainscoherency between various cache units 3206 and 3204A-3204N.

In at least one embodiment, processor 3200 may also include a set of oneor more bus controller units 3216 and a system agent core 3210. In atleast one embodiment, one or more bus controller units 3216 manage a setof peripheral buses, such as one or more PCI or PCI express busses. Inat least one embodiment, system agent core 3210 provides managementfunctionality for various processor components. In at least oneembodiment, system agent core 3210 includes one or more integratedmemory controllers 3214 to manage access to various external memorydevices (not shown).

In at least one embodiment, one or more of processor cores 3202A-3202Ninclude support for simultaneous multi-threading. In at least oneembodiment, system agent core 3210 includes components for coordinatingand operating cores 3202A-3202N during multi-threaded processing. In atleast one embodiment, system agent core 3210 may additionally include apower control unit (PCU), which includes logic and components toregulate one or more power states of processor cores 3202A-3202N andgraphics processor 3208.

In at least one embodiment, processor 3200 additionally includesgraphics processor 3208 to execute graphics processing operations. In atleast one embodiment, graphics processor 3208 couples with shared cacheunits 3206, and system agent core 3210, including one or more integratedmemory controllers 3214. In at least one embodiment, system agent core3210 also includes a display controller 3211 to drive graphics processoroutput to one or more coupled displays. In at least one embodiment,display controller 3211 may also be a separate module coupled withgraphics processor 3208 via at least one interconnect, or may beintegrated within graphics processor 3208.

In at least one embodiment, a ring based interconnect unit 3212 is usedto couple internal components of processor 3200. In at least oneembodiment, an alternative interconnect unit may be used, such as apoint-to-point interconnect, a switched interconnect, or othertechniques. In at least one embodiment, graphics processor 3208 coupleswith ring interconnect 3212 via an I/O link 3213.

In at least one embodiment, I/O link 3213 represents at least one ofmultiple varieties of I/O interconnects, including an on package I/Ointerconnect which facilitates communication between various processorcomponents and a high-performance embedded memory module 3218, such asan eDRAM module. In at least one embodiment, each of processor cores3202A-3202N and graphics processor 3208 use embedded memory modules 3218as a shared Last Level Cache.

In at least one embodiment, processor cores 3202A-3202N are homogenouscores executing a common instruction set architecture. In at least oneembodiment, processor cores 3202A-3202N are heterogeneous in terms ofinstruction set architecture (ISA), where one or more of processor cores3202A-3202N execute a common instruction set, while one or more othercores of processor cores 3202A-32-02N executes a subset of a commoninstruction set or a different instruction set. In at least oneembodiment, processor cores 3202A-3202N are heterogeneous in terms ofmicroarchitecture, where one or more cores having a relatively higherpower consumption couple with one or more power cores having a lowerpower consumption. In at least one embodiment, processor 3200 can beimplemented on one or more chips or as an SoC integrated circuit. In atleast one embodiment, at least one component shown or described withrespect to FIG. 32 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-15B.

FIG. 33 is a block diagram of a graphics processor 3300, which may be adiscrete graphics processing unit, or may be a graphics processorintegrated with a plurality of processing cores. In at least oneembodiment, graphics processor 3300 communicates via a memory mapped I/Ointerface to registers on graphics processor 3300 and with commandsplaced into memory. In at least one embodiment, graphics processor 3300includes a memory interface 3314 to access memory. In at least oneembodiment, memory interface 3314 is an interface to local memory, oneor more internal caches, one or more shared external caches, and/or tosystem memory.

In at least one embodiment, graphics processor 3300 also includes adisplay controller 3302 to drive display output data to a display device3320. In at least one embodiment, display controller 3302 includeshardware for one or more overlay planes for display device 3320 andcomposition of multiple layers of video or user interface elements. Inat least one embodiment, display device 3320 can be an internal orexternal display device. In at least one embodiment, display device 3320is a head mounted display device, such as a virtual reality (VR) displaydevice or an augmented reality (AR) display device. In at least oneembodiment, graphics processor 3300 includes a video codec engine 3306to encode, decode, or transcode media to, from, or between one or moremedia encoding formats, including, but not limited to Moving PictureExperts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC)formats such as H.264/MPEG-4 AVC, as well as the Society of MotionPicture & Television Engineers (SMPTE) 421M/VC-1, and Joint PhotographicExperts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG)formats.

In at least one embodiment, graphics processor 3300 includes a blockimage transfer (BLIT) engine 3304 to perform two-dimensional (2D)rasterizer operations including, for example, bit-boundary blocktransfers. However, in at least one embodiment, 2D graphics operationsare performed using one or more components of graphics processing engine(GPE) 3310. In at least one embodiment, GPE 3310 is a compute engine forperforming graphics operations, including three-dimensional (3D)graphics operations and media operations.

In at least one embodiment, GPE 3310 includes a 3D pipeline 3312 forperforming 3D operations, such as rendering three-dimensional images andscenes using processing functions that act upon 3D primitive shapes(e.g., rectangle, triangle, etc.). 3D pipeline 3312 includesprogrammable and fixed function elements that perform various tasksand/or spawn execution threads to a 3D/Media sub-system 3315. While 3Dpipeline 3312 can be used to perform media operations, in at least oneembodiment, GPE 3310 also includes a media pipeline 3316 that is used toperform media operations, such as video post-processing and imageenhancement.

In at least one embodiment, media pipeline 3316 includes fixed functionor programmable logic units to perform one or more specialized mediaoperations, such as video decode acceleration, video de-interlacing, andvideo encode acceleration in place of, or on behalf of video codecengine 3306. In at least one embodiment, media pipeline 3316additionally includes a thread spawning unit to spawn threads forexecution on 3D/Media sub-system 3315. In at least one embodiment,spawned threads perform computations for media operations on one or moregraphics execution units included in 3D/Media sub-system 3315.

In at least one embodiment, 3D/Media subsystem 3315 includes logic forexecuting threads spawned by 3D pipeline 3312 and media pipeline 3316.In at least one embodiment, 3D pipeline 3312 and media pipeline 3316send thread execution requests to 3D/Media subsystem 3315, whichincludes thread dispatch logic for arbitrating and dispatching variousrequests to available thread execution resources. In at least oneembodiment, execution resources include an array of graphics executionunits to process 3D and media threads. In at least one embodiment,3D/Media subsystem 3315 includes one or more internal caches for threadinstructions and data. In at least one embodiment, subsystem 3315 alsoincludes shared memory, including registers and addressable memory, toshare data between threads and to store output data. In at least oneembodiment, at least one component shown or described with respect toFIG. 33 is used to implement techniques and/or functions described inconnection with FIGS. 1-15B.

FIG. 34 is a block diagram of a graphics processing engine 3410 of agraphics processor in accordance with at least one embodiment. In atleast one embodiment, graphics processing engine (GPE) 3410 is a versionof GPE 3310 shown in FIG. 33 . In at least one embodiment, mediapipeline 3416 is optional and may not be explicitly included within GPE3410. In at least one embodiment, a separate media and/or imageprocessor is coupled to GPE 3410.

In at least one embodiment, GPE 3410 is coupled to or includes a commandstreamer 3403, which provides a command stream to 3D pipeline 3412and/or media pipelines 3416. In at least one embodiment, commandstreamer 3403 is coupled to memory, which can be system memory, or oneor more of internal cache memory and shared cache memory. In at leastone embodiment, command streamer 3403 receives commands from memory andsends commands to 3D pipeline 3412 and/or media pipeline 3416. In atleast one embodiment, commands are instructions, primitives, ormicro-operations fetched from a ring buffer, which stores commands for3D pipeline 3412 and media pipeline 3416. In at least one embodiment, aring buffer can additionally include batch command buffers storingbatches of multiple commands. In at least one embodiment, commands for3D pipeline 3412 can also include references to data stored in memory,such as but not limited to vertex and geometry data for 3D pipeline 3412and/or image data and memory objects for media pipeline 3416. In atleast one embodiment, 3D pipeline 3412 and media pipeline 3416 processcommands and data by performing operations or by dispatching one or moreexecution threads to a graphics core array 3414. In at least oneembodiment graphics core array 3414 includes one or more blocks ofgraphics cores (e.g., graphics core(s) 3415A, graphics core(s) 3415B),each block including one or more graphics cores. In at least oneembodiment, each graphics core includes a set of graphics executionresources that includes general-purpose and graphics specific executionlogic to perform graphics and compute operations, as well as fixedfunction texture processing and/or machine learning and artificialintelligence acceleration logic.

In at least one embodiment, 3D pipeline 3412 includes fixed function andprogrammable logic to process one or more shader programs, such asvertex shaders, geometry shaders, pixel shaders, fragment shaders,compute shaders, or other shader programs, by processing instructionsand dispatching execution threads to graphics core array 3414. In atleast one embodiment, graphics core array 3414 provides a unified blockof execution resources for use in processing shader programs. In atleast one embodiment, multi-purpose execution logic (e.g., executionunits) within graphics core(s) 3415A-3415B of graphic core array 3414includes support for various 3D API shader languages and can executemultiple simultaneous execution threads associated with multipleshaders.

In at least one embodiment, graphics core array 3414 also includesexecution logic to perform media functions, such as video and/or imageprocessing. In at least one embodiment, execution units additionallyinclude general-purpose logic that is programmable to perform parallelgeneral-purpose computational operations, in addition to graphicsprocessing operations.

In at least one embodiment, output data generated by threads executingon graphics core array 3414 can output data to memory in a unifiedreturn buffer (URB) 3418. URB 3418 can store data for multiple threads.In at least one embodiment, URB 3418 may be used to send data betweendifferent threads executing on graphics core array 3414. In at least oneembodiment, URB 3418 may additionally be used for synchronizationbetween threads on graphics core array 3414 and fixed function logicwithin shared function logic 3420.

In at least one embodiment, graphics core array 3414 is scalable, suchthat graphics core array 3414 includes a variable number of graphicscores, each having a variable number of execution units based on atarget power and performance level of GPE 3410. In at least oneembodiment, execution resources are dynamically scalable, such thatexecution resources may be enabled or disabled as needed.

In at least one embodiment, graphics core array 3414 is coupled toshared function logic 3420 that includes multiple resources that areshared between graphics cores in graphics core array 3414. In at leastone embodiment, shared functions performed by shared function logic 3420are embodied in hardware logic units that provide specializedsupplemental functionality to graphics core array 3414. In at least oneembodiment, shared function logic 3420 includes but is not limited tosampler 3421, math 3422, and inter-thread communication (ITC) 3423logic. In at least one embodiment, one or more cache(s) 3425 are inincluded in or couple to shared function logic 3420.

In at least one embodiment, a shared function is used if demand for aspecialized function is insufficient for inclusion within graphics corearray 3414. In at least one embodiment, a single instantiation of aspecialized function is used in shared function logic 3420 and sharedamong other execution resources within graphics core array 3414. In atleast one embodiment, specific shared functions within shared functionlogic 3420 that are used extensively by graphics core array 3414 may beincluded within shared function logic 3416 within graphics core array3414. In at least one embodiment, shared function logic 3416 withingraphics core array 3414 can include some or all logic within sharedfunction logic 3420. In at least one embodiment, all logic elementswithin shared function logic 3420 may be duplicated within sharedfunction logic 3416 of graphics core array 3414. In at least oneembodiment, shared function logic 3420 is excluded in favor of sharedfunction logic 3416 within graphics core array 3414. In at least oneembodiment, at least one component shown or described with respect toFIG. 34 is used to implement techniques and/or functions described inconnection with FIGS. 1-15B.

FIG. 35 is a block diagram of hardware logic of a graphics processorcore 3500, according to at least one embodiment described herein. In atleast one embodiment, graphics processor core 3500 is included within agraphics core array. In at least one embodiment, graphics processor core3500, sometimes referred to as a core slice, can be one or multiplegraphics cores within a modular graphics processor. In at least oneembodiment, graphics processor core 3500 is exemplary of one graphicscore slice, and a graphics processor as described herein may includemultiple graphics core slices based on target power and performanceenvelopes. In at least one embodiment, each graphics core 3500 caninclude a fixed function block 3530 coupled with multiple sub-cores3501A-3501F, also referred to as sub-slices, that include modular blocksof general-purpose and fixed function logic.

In at least one embodiment, fixed function block 3530 includes ageometry/fixed function pipeline 3536 that can be shared by allsub-cores in graphics processor 3500, for example, in lower performanceand/or lower power graphics processor implementations. In at least oneembodiment, geometry/fixed function pipeline 3536 includes a 3D fixedfunction pipeline, a video front-end unit, a thread spawner and threaddispatcher, and a unified return buffer manager, which manages unifiedreturn buffers.

In at least one embodiment fixed function block 3530 also includes agraphics SoC interface 3537, a graphics microcontroller 3538, and amedia pipeline 3539. Graphics SoC interface 3537 provides an interfacebetween graphics core 3500 and other processor cores within a system ona chip integrated circuit. In at least one embodiment, graphicsmicrocontroller 3538 is a programmable sub-processor that isconfigurable to manage various functions of graphics processor 3500,including thread dispatch, scheduling, and pre-emption. In at least oneembodiment, media pipeline 3539 includes logic to facilitate decoding,encoding, pre-processing, and/or post-processing of multimedia data,including image and video data. In at least one embodiment, mediapipeline 3539 implements media operations via requests to compute orsampling logic within sub-cores 3501-3501F.

In at least one embodiment, SoC interface 3537 enables graphics core3500 to communicate with general-purpose application processor cores(e.g., CPUs) and/or other components within an SoC, including memoryhierarchy elements such as a shared last level cache memory, system RAM,and/or embedded on-chip or on-package DRAM. In at least one embodiment,SoC interface 3537 can also enable communication with fixed functiondevices within an SoC, such as camera imaging pipelines, and enables useof and/or implements global memory atomics that may be shared betweengraphics core 3500 and CPUs within an SoC. In at least one embodiment,SoC interface 3537 can also implement power management controls forgraphics core 3500 and enable an interface between a clock domain ofgraphic core 3500 and other clock domains within an SoC. In at least oneembodiment, SoC interface 3537 enables receipt of command buffers from acommand streamer and global thread dispatcher that are configured toprovide commands and instructions to each of one or more graphics coreswithin a graphics processor. In at least one embodiment, commands andinstructions can be dispatched to media pipeline 3539, when mediaoperations are to be performed, or a geometry and fixed functionpipeline (e.g., geometry and fixed function pipeline 3536, geometry andfixed function pipeline 3514) when graphics processing operations are tobe performed.

In at least one embodiment, graphics microcontroller 3538 can beconfigured to perform various scheduling and management tasks forgraphics core 3500. In at least one embodiment, graphics microcontroller3538 can perform graphics and/or compute workload scheduling on variousgraphics parallel engines within execution unit (EU) arrays 3502A-3502F,3504A-3504F within sub-cores 3501A-3501F. In at least one embodiment,host software executing on a CPU core of an SoC including graphics core3500 can submit workloads one of multiple graphic processor doorbells,which invokes a scheduling operation on an appropriate graphics engine.In at least one embodiment, scheduling operations include determiningwhich workload to run next, submitting a workload to a command streamer,pre-empting existing workloads running on an engine, monitoring progressof a workload, and notifying host software when a workload is complete.In at least one embodiment, graphics microcontroller 3538 can alsofacilitate low-power or idle states for graphics core 3500, providinggraphics core 3500 with an ability to save and restore registers withingraphics core 3500 across low-power state transitions independently froman operating system and/or graphics driver software on a system.

In at least one embodiment, graphics core 3500 may have greater than orfewer than illustrated sub-cores 3501A-3501F, up to N modular sub-cores.For each set of N sub-cores, in at least one embodiment, graphics core3500 can also include shared function logic 3510, shared and/or cachememory 3512, a geometry/fixed function pipeline 3514, as well asadditional fixed function logic 3516 to accelerate various graphics andcompute processing operations. In at least one embodiment, sharedfunction logic 3510 can include logic units (e.g., sampler, math, and/orinter-thread communication logic) that can be shared by each N sub-coreswithin graphics core 3500. Shared and/or cache memory 3512 can be alast-level cache for N sub-cores 3501A-3501F within graphics core 3500and can also serve as shared memory that is accessible by multiplesub-cores. In at least one embodiment, geometry/fixed function pipeline3514 can be included instead of geometry/fixed function pipeline 3536within fixed function block 3530 and can include same or similar logicunits.

In at least one embodiment, graphics core 3500 includes additional fixedfunction logic 3516 that can include various fixed function accelerationlogic for use by graphics core 3500. In at least one embodiment,additional fixed function logic 3516 includes an additional geometrypipeline for use in position only shading. In position-only shading, atleast two geometry pipelines exist, whereas in a full geometry pipelinewithin geometry/fixed function pipeline 3516, 3536, and a cull pipeline,which is an additional geometry pipeline which may be included withinadditional fixed function logic 3516. In at least one embodiment, cullpipeline is a trimmed down version of a full geometry pipeline. In atleast one embodiment, a full pipeline and a cull pipeline can executedifferent instances of an application, each instance having a separatecontext. In at least one embodiment, position only shading can hide longcull runs of discarded triangles, enabling shading to be completedearlier in some instances. For example, in at least one embodiment, cullpipeline logic within additional fixed function logic 3516 can executeposition shaders in parallel with a main application and generallygenerates critical results faster than a full pipeline, as cull pipelinefetches and shades position attribute of vertices, without performingrasterization and rendering of pixels to a frame buffer. In at least oneembodiment, cull pipeline can use generated critical results to computevisibility information for all triangles without regard to whether thosetriangles are culled. In at least one embodiment, full pipeline (whichin this instance may be referred to as a replay pipeline) can consumevisibility information to skip culled triangles to shade only visibletriangles that are finally passed to a rasterization phase.

In at least one embodiment, additional fixed function logic 3516 canalso include machine-learning acceleration logic, such as fixed functionmatrix multiplication logic, for implementations including optimizationsfor machine learning training or inferencing.

In at least one embodiment, within each graphics sub-core 3501A-3501Fincludes a set of execution resources that may be used to performgraphics, media, and compute operations in response to requests bygraphics pipeline, media pipeline, or shader programs. In at least oneembodiment, graphics sub-cores 3501A-3501F include multiple EU arrays3502A-3502F, 3504A-3504F, thread dispatch and inter-thread communication(TD/IC) logic 3503A-3503F, a 3D (e.g., texture) sampler 3505A-3505F, amedia sampler 3506A-3506F, a shader processor 3507A-3507F, and sharedlocal memory (SLM) 3508A-3508F. EU arrays 3502A-3502F, 3504A-3504F eachinclude multiple execution units, which are general-purpose graphicsprocessing units capable of performing floating-point andinteger/fixed-point logic operations in service of a graphics, media, orcompute operation, including graphics, media, or compute shaderprograms. In at least one embodiment, TD/IC logic 3503A-3503F performslocal thread dispatch and thread control operations for execution unitswithin a sub-core and facilitate communication between threads executingon execution units of a sub-core. In at least one embodiment, 3D sampler3505A-3505F can read texture or other 3D graphics related data intomemory. In at least one embodiment, 3D sampler can read texture datadifferently based on a configured sample state and texture formatassociated with a given texture. In at least one embodiment, mediasampler 3506A-3506F can perform similar read operations based on a typeand format associated with media data. In at least one embodiment, eachgraphics sub-core 3501A-3501F can alternately include a unified 3D andmedia sampler. In at least one embodiment, threads executing onexecution units within each of sub-cores 3501A-3501F can make use ofshared local memory 3508A-3508F within each sub-core, to enable threadsexecuting within a thread group to execute using a common pool ofon-chip memory. In at least one embodiment, at least one component shownor described with respect to FIG. 35 is used to implement techniquesand/or functions described in connection with FIGS. 1-15B.

FIGS. 36A-36B illustrate thread execution logic 3600 including an arrayof processing elements of a graphics processor core according to atleast one embodiment. FIG. 36A illustrates at least one embodiment, inwhich thread execution logic 3600 is used. FIG. 36B illustratesexemplary internal details of an execution unit, according to at leastone embodiment.

As illustrated in FIG. 36A, in at least one embodiment, thread executionlogic 3600 includes a shader processor 3602, a thread dispatcher 3604,instruction cache 3606, a scalable execution unit array including aplurality of execution units 3608A-3608N, a sampler 3610, a data cache3612, and a data port 3614. In at least one embodiment a scalableexecution unit array can dynamically scale by enabling or disabling oneor more execution units (e.g., any of execution unit 3608A, 3608B,3608C, 3608D, through 3608N-1 and 3608N) based on computationalrequirements of a workload, for example. In at least one embodiment,scalable execution units are interconnected via an interconnect fabricthat links to each of execution unit. In at least one embodiment, threadexecution logic 3600 includes one or more connections to memory, such assystem memory or cache memory, through one or more of instruction cache3606, data port 3614, sampler 3610, and execution units 3608A-3608N. Inat least one embodiment, each execution unit (e.g., 3608A) is astand-alone programmable general-purpose computational unit that iscapable of executing multiple simultaneous hardware threads whileprocessing multiple data elements in parallel for each thread. In atleast one embodiment, array of execution units 3608A-3608N is scalableto include any number individual execution units.

In at least one embodiment, execution units 3608A-3608N are primarilyused to execute shader programs. In at least one embodiment, shaderprocessor 3602 can process various shader programs and dispatchexecution threads associated with shader programs via a threaddispatcher 3604. In at least one embodiment, thread dispatcher 3604includes logic to arbitrate thread initiation requests from graphics andmedia pipelines and instantiate requested threads on one or moreexecution units in execution units 3608A-3608N. For example, in at leastone embodiment, a geometry pipeline can dispatch vertex, tessellation,or geometry shaders to thread execution logic for processing. In atleast one embodiment, thread dispatcher 3604 can also process runtimethread spawning requests from executing shader programs.

In at least one embodiment, execution units 3608A-3608N support aninstruction set that includes native support for many standard 3Dgraphics shader instructions, such that shader programs from graphicslibraries (e.g., Direct 3D and OpenGL) are executed with a minimaltranslation. In at least one embodiment, execution units support vertexand geometry processing (e.g., vertex programs, geometry programs,vertex shaders), pixel processing (e.g., pixel shaders, fragmentshaders) and general-purpose processing (e.g., compute and mediashaders). In at least one embodiment, each of execution units3608A-3608N, which include one or more arithmetic logic units (ALUs), iscapable of multi-issue single instruction multiple data (SIMD) executionand multi-threaded operation enables an efficient execution environmentdespite higher latency memory accesses. In at least one embodiment, eachhardware thread within each execution unit has a dedicatedhigh-bandwidth register file and associated independent thread-state. Inat least one embodiment, execution is multi-issue per clock to pipelinescapable of integer, single and double precision floating pointoperations, SIMD branch capability, logical operations, transcendentaloperations, and other miscellaneous operations. In at least oneembodiment, while waiting for data from memory or one of sharedfunctions, dependency logic within execution units 3608A-3608N causes awaiting thread to sleep until requested data has been returned. In atleast one embodiment, while a waiting thread is sleeping, hardwareresources may be devoted to processing other threads. For example, in atleast one embodiment, during a delay associated with a vertex shaderoperation, an execution unit can perform operations for a pixel shader,fragment shader, or another type of shader program, including adifferent vertex shader.

In at least one embodiment, each execution unit in execution units3608A-3608N operates on arrays of data elements. In at least oneembodiment, a number of data elements is “execution size,” or number ofchannels for an instruction. In at least one embodiment, an executionchannel is a logical unit of execution for data element access, masking,and flow control within instructions. In at least one embodiment, anumber of channels may be independent of a number of physical ArithmeticLogic Units (ALUs) or Floating Point Units (FPUs) for a particulargraphics processor. In at least one embodiment, execution units3608A-3608N support integer and floating-point data types.

In at least one embodiment, an execution unit instruction set includesSIMD instructions. In at least one embodiment, various data elements canbe stored as a packed data type in a register and execution unit willprocess various elements based on data size of elements. For example, inat least one embodiment, when operating on a 256-bit wide vector, 256bits of a vector are stored in a register and an execution unit operateson a vector as four separate 64-bit packed data elements (Quad-Word (QW)size data elements), eight separate 32-bit packed data elements (DoubleWord (DW) size data elements), sixteen separate 16-bit packed dataelements (Word (W) size data elements), or thirty-two separate 8-bitdata elements (byte (B) size data elements). However, in at least oneembodiment, different vector widths and register sizes are possible.

In at least one embodiment, one or more execution units can be combinedinto a fused execution unit 3609A-3609N having thread control logic(3607A-3607N) that is common to fused EUs. In at least one embodiment,multiple EUs can be fused into an EU group. In at least one embodiment,each EU in fused EU group can be configured to execute a separate SIMDhardware thread. Th number of EUs in a fused EU group can vary accordingto various embodiments. In at least one embodiment, various SIMD widthscan be performed per-EU, including but not limited to SIMD8, SIMD16, andSIMD32. In at least one embodiment, each fused graphics execution unit3609A-3609N includes at least two execution units. For example, in atleast one embodiment, fused execution unit 3609A includes a first EU3608A, second EU 3608B, and thread control logic 3607A that is common tofirst EU 3608A and second EU 3608B. In at least one embodiment, threadcontrol logic 3607A controls threads executed on fused graphicsexecution unit 3609A, allowing each EU within fused execution units3609A-3609N to execute using a common instruction pointer register.

In at least one embodiment, one or more internal instruction caches(e.g., 3606) are included in thread execution logic 3600 to cache threadinstructions for execution units. In at least one embodiment, one ormore data caches (e.g., 3612) are included to cache thread data duringthread execution. In at least one embodiment, a sampler 3610 is includedto provide texture sampling for 3D operations and media sampling formedia operations. In at least one embodiment, sampler 3610 includesspecialized texture or media sampling functionality to process textureor media data during sampling process before providing sampled data toan execution unit.

During execution, in at least one embodiment, graphics and mediapipelines send thread initiation requests to thread execution logic 3600via thread spawning and dispatch logic. In at least one embodiment, oncea group of geometric objects has been processed and rasterized intopixel data, pixel processor logic (e.g., pixel shader logic, fragmentshader logic, etc.) within shader processor 3602 is invoked to furthercompute output information and cause results to be written to outputsurfaces (e.g., color buffers, depth buffers, stencil buffers, etc.). Inat least one embodiment, a pixel shader or fragment shader calculatesvalues of various vertex attributes that are to be interpolated across arasterized object. In at least one embodiment, pixel processor logicwithin shader processor 3602 then executes an application programminginterface (API)-supplied pixel or fragment shader program. In at leastone embodiment, to execute a shader program, shader processor 3602dispatches threads to an execution unit (e.g., 3608A) via threaddispatcher 3604. In at least one embodiment, shader processor 3602 usestexture sampling logic in sampler 3610 to access texture data in texturemaps stored in memory. In at least one embodiment, arithmetic operationson texture data and input geometry data compute pixel color data foreach geometric fragment, or discards one or more pixels from furtherprocessing.

In at least one embodiment, data port 3614 provides a memory accessmechanism for thread execution logic 3600 to output processed data tomemory for further processing on a graphics processor output pipeline.In at least one embodiment, data port 3614 includes or couples to one ormore cache memories (e.g., data cache 3612) to cache data for memoryaccess via a data port.

As illustrated in FIG. 36B, in at least one embodiment, a graphicsexecution unit 3608 can include an instruction fetch unit 3637, ageneral register file array (GRF) 3624, an architectural register filearray (ARF) 3626, a thread arbiter 3622, a send unit 3630, a branch unit3632, a set of SIMD floating point units (FPUs) 3634, and In at leastone embodiment a set of dedicated integer SIMD ALUs 3635. In at leastone embodiment, GRF 3624 and ARF 3626 includes a set of general registerfiles and architecture register files associated with each simultaneoushardware thread that may be active in graphics execution unit 3608. Inat least one embodiment, per thread architectural state is maintained inARF 3626, while data used during thread execution is stored in GRF 3624.In at least one embodiment, execution state of each thread, includinginstruction pointers for each thread, can be held in thread-specificregisters in ARF 3626.

In at least one embodiment, graphics execution unit 3608 has anarchitecture that is a combination of Simultaneous Multi-Threading (SMT)and fine-grained Interleaved Multi-Threading (IMT). In at least oneembodiment, architecture has a modular configuration that can befine-tuned at design time based on a target number of simultaneousthreads and number of registers per execution unit, where execution unitresources are divided across logic used to execute multiple simultaneousthreads.

In at least one embodiment, graphics execution unit 3608 can co-issuemultiple instructions, which may each be different instructions. In atleast one embodiment, thread arbiter 3622 of graphics execution unitthread 3608 can dispatch instructions to one of send unit 3630, branchunit 3642, or SIMD FPU(s) 3634 for execution. In at least oneembodiment, each execution thread can access 128 general-purposeregisters within GRF 3624, where each register can store 32 bytes,accessible as a SIMD 8-element vector of 32-bit data elements. In atleast one embodiment, each execution unit thread has access to 4 Kbyteswithin GRF 3624, although embodiments are not so limited, and greater orfewer register resources may be provided in other embodiments. In atleast one embodiment, up to seven threads can execute simultaneously,although a number of threads per execution unit can also vary accordingto embodiments. In at least one embodiment, in which seven threads mayaccess 4 Kbytes, GRF 3624 can store a total of 28 Kbytes. In at leastone embodiment, flexible addressing modes can permit registers to beaddressed together to build effectively wider registers or to representstrided rectangular block data structures.

In at least one embodiment, memory operations, sampler operations, andother longer-latency system communications are dispatched via “send”instructions that are executed by message passing send unit 3630. In atleast one embodiment, branch instructions are dispatched to a dedicatedbranch unit 3632 to facilitate SIMD divergence and eventual convergence.

In at least one embodiment graphics execution unit 3608 includes one ormore SIMD floating point units (FPU(s)) 3634 to perform floating-pointoperations. In at least one embodiment, FPU(s) 3634 also support integercomputation. In at least one embodiment FPU(s) 3634 can SIMD execute upto M number of 32-bit floating-point (or integer) operations, or SIMDexecute up to 2M 16-bit integer or 16-bit floating-point operations. Inat least one embodiment, at least one of FPU(s) provides extended mathcapability to support high-throughput transcendental math functions anddouble precision 64-bit floating-point. In at least one embodiment, aset of 8-bit integer SIMD ALUs 3635 are also present, and may bespecifically optimized to perform operations associated with machinelearning computations.

In at least one embodiment, arrays of multiple instances of graphicsexecution unit 3608 can be instantiated in a graphics sub-core grouping(e.g., a sub-slice). In at least one embodiment execution unit 3608 canexecute instructions across a plurality of execution channels. In atleast one embodiment, each thread executed on graphics execution unit3608 is executed on a different channel. In at least one embodiment, atleast one component shown or described with respect to FIGS. 36A-36B isused to implement techniques and/or functions described in connectionwith FIGS. 1-15B.

FIG. 37 illustrates a parallel processing unit (“PPU”) 3700, accordingto at least one embodiment. In at least one embodiment, PPU 3700 isconfigured with machine-readable code that, if executed by PPU 3700,causes PPU 3700 to perform some or all of processes and techniquesdescribed throughout this disclosure. In at least one embodiment, PPU3700 is a multi-threaded processor that is implemented on one or moreintegrated circuit devices and that utilizes multithreading as alatency-hiding technique designed to process computer-readableinstructions (also referred to as machine-readable instructions orsimply instructions) on multiple threads in parallel. In at least oneembodiment, a thread refers to a thread of execution and is aninstantiation of a set of instructions configured to be executed by PPU3700. In at least one embodiment, PPU 3700 is a graphics processing unit(“GPU”) configured to implement a graphics rendering pipeline forprocessing three-dimensional (“3D”) graphics data in order to generatetwo-dimensional (“2D”) image data for display on a display device suchas a liquid crystal display (“LCD”) device. In at least one embodiment,PPU 3700 is utilized to perform computations such as linear algebraoperations and machine-learning operations. FIG. 37 illustrates anexample parallel processor for illustrative purposes only and should beconstrued as a non-limiting example of processor architecturescontemplated within scope of this disclosure and that any suitableprocessor may be employed to supplement and/or substitute for same.

In at least one embodiment, one or more PPUs 3700 are configured toaccelerate High Performance Computing (“HPC”), data center, and machinelearning applications. In at least one embodiment, PPU 3700 isconfigured to accelerate deep learning systems and applicationsincluding following non-limiting examples: autonomous vehicle platforms,deep learning, high-accuracy speech, image, text recognition systems,intelligent video analytics, molecular simulations, drug discovery,disease diagnosis, weather forecasting, big data analytics, astronomy,molecular dynamics simulation, financial modeling, robotics, factoryautomation, real-time language translation, online search optimizations,and personalized user recommendations, and more.

In at least one embodiment, PPU 3700 includes, without limitation, anInput/Output (“I/O”) unit 3706, a front-end unit 3710, a scheduler unit3712, a work distribution unit 3714, a hub 3716, a crossbar (“Xbar”)3720, one or more general processing clusters (“GPCs”) 3718, and one ormore partition units (“memory partition units”) 3722. In at least oneembodiment, PPU 3700 is connected to a host processor or other PPUs 3700via one or more high-speed GPU interconnects (“GPU interconnects”) 3708.In at least one embodiment, PPU 3700 is connected to a host processor orother peripheral devices via an interconnect 3702. In at least oneembodiment, PPU 3700 is connected to a local memory comprising one ormore memory devices (“memory”) 3704. In at least one embodiment, memorydevices 3704 include, without limitation, one or more dynamic randomaccess memory (“DRAM”) devices. In at least one embodiment, one or moreDRAM devices are configured and/or configurable as high-bandwidth memory(“HBM”) subsystems, with multiple DRAM dies stacked within each device.

In at least one embodiment, high-speed GPU interconnect 3708 may referto a wire-based multi-lane communications link that is used by systemsto scale and include one or more PPUs 3700 combined with one or morecentral processing units (“CPUs”), supports cache coherence between PPUs3700 and CPUs, and CPU mastering. In at least one embodiment, dataand/or commands are transmitted by high-speed GPU interconnect 3708through hub 3716 to/from other units of PPU 3700 such as one or morecopy engines, video encoders, video decoders, power management units,and other components which may not be explicitly illustrated in FIG. 37.

In at least one embodiment, I/O unit 3706 is configured to transmit andreceive communications (e.g., commands, data) from a host processor (notillustrated in FIG. 37 ) over system bus 3702. In at least oneembodiment, I/O unit 3706 communicates with host processor directly viasystem bus 3702 or through one or more intermediate devices such as amemory bridge. In at least one embodiment, I/O unit 3706 may communicatewith one or more other processors, such as one or more of PPUs 3700 viasystem bus 3702. In at least one embodiment, I/O unit 3706 implements aPeripheral Component Interconnect Express (“PCIe”) interface forcommunications over a PCIe bus. In at least one embodiment, I/O unit3706 implements interfaces for communicating with external devices.

In at least one embodiment, I/O unit 3706 decodes packets received viasystem bus 3702. In at least one embodiment, at least some packetsrepresent commands configured to cause PPU 3700 to perform variousoperations. In at least one embodiment, I/O unit 3706 transmits decodedcommands to various other units of PPU 3700 as specified by commands. Inat least one embodiment, commands are transmitted to front-end unit 3710and/or transmitted to hub 3716 or other units of PPU 3700 such as one ormore copy engines, a video encoder, a video decoder, a power managementunit, etc. (not explicitly illustrated in FIG. 37 ). In at least oneembodiment, I/O unit 3706 is configured to route communications betweenand among various logical units of PPU 3700.

In at least one embodiment, a program executed by host processor encodesa command stream in a buffer that provides workloads to PPU 3700 forprocessing. In at least one embodiment, a workload comprisesinstructions and data to be processed by those instructions. In at leastone embodiment, buffer is a region in a memory that is accessible (e.g.,read/write) by both host processor and PPU 3700—a host interface unitmay be configured to access buffer in a system memory connected tosystem bus 3702 via memory requests transmitted over system bus 3702 byI/O unit 3706. In at least one embodiment, host processor writes commandstream to buffer and then transmits a pointer to start of command streamto PPU 3700 such that front-end unit 3710 receives pointers to one ormore command streams and manages one or more command streams, readingcommands from command streams and forwarding commands to various unitsof PPU 3700.

In at least one embodiment, front-end unit 3710 is coupled to schedulerunit 3712 that configures various GPCs 3718 to process tasks defined byone or more command streams. In at least one embodiment, scheduler unit3712 is configured to track state information related to various tasksmanaged by scheduler unit 3712 where state information may indicatewhich of GPCs 3718 a task is assigned to, whether task is active orinactive, a priority level associated with task, and so forth. In atleast one embodiment, scheduler unit 3712 manages execution of aplurality of tasks on one or more of GPCs 3718.

In at least one embodiment, scheduler unit 3712 is coupled to workdistribution unit 3714 that is configured to dispatch tasks forexecution on GPCs 3718. In at least one embodiment, work distributionunit 3714 tracks a number of scheduled tasks received from schedulerunit 3712 and work distribution unit 3714 manages a pending task pooland an active task pool for each of GPCs 3718. In at least oneembodiment, pending task pool comprises a number of slots (e.g., 32slots) that contain tasks assigned to be processed by a particular GPC3718; active task pool may comprise a number of slots (e.g., 4 slots)for tasks that are actively being processed by GPCs 3718 such that asone of GPCs 3718 completes execution of a task, that task is evictedfrom active task pool for GPC 3718 and one of other tasks from pendingtask pool is selected and scheduled for execution on GPC 3718. In atleast one embodiment, if an active task is idle on GPC 3718, such aswhile waiting for a data dependency to be resolved, then active task isevicted from GPC 3718 and returned to pending task pool while anothertask in pending task pool is selected and scheduled for execution on GPC3718.

In at least one embodiment, work distribution unit 3714 communicateswith one or more GPCs 3718 via XBar 3720. In at least one embodiment,XBar 3720 is an interconnect network that couples many of units of PPU3700 to other units of PPU 3700 and can be configured to couple workdistribution unit 3714 to a particular GPC 3718. In at least oneembodiment, one or more other units of PPU 3700 may also be connected toXBar 3720 via hub 3716.

In at least one embodiment, tasks are managed by scheduler unit 3712 anddispatched to one of GPCs 3718 by work distribution unit 3714. GPC 3718is configured to process task and generate results. In at least oneembodiment, results may be consumed by other tasks within GPC 3718,routed to a different GPC 3718 via XBar 3720, or stored in memory 3704.In at least one embodiment, results can be written to memory 3704 viapartition units 3722, which implement a memory interface for reading andwriting data to/from memory 3704. In at least one embodiment, resultscan be transmitted to another PPU 3704 or CPU via high-speed GPUinterconnect 3708. In at least one embodiment, PPU 3700 includes,without limitation, a number U of partition units 3722 that is equal tonumber of separate and distinct memory devices 3704 coupled to PPU 3700.In at least one embodiment, partition unit 3722 will be described inmore detail herein in conjunction with FIG. 39 .

In at least one embodiment, a host processor executes a driver kernelthat implements an application programming interface (“API”) thatenables one or more applications executing on host processor to scheduleoperations for execution on PPU 3700. In at least one embodiment,multiple compute applications are simultaneously executed by PPU 3700and PPU 3700 provides isolation, quality of service (“QoS”), andindependent address spaces for multiple compute applications. In atleast one embodiment, an application generates instructions (e.g., inform of API calls) that cause driver kernel to generate one or moretasks for execution by PPU 3700 and driver kernel outputs tasks to oneor more streams being processed by PPU 3700. In at least one embodiment,each task comprises one or more groups of related threads, which may bereferred to as a warp. In at least one embodiment, a warp comprises aplurality of related threads (e.g., 32 threads) that can be executed inparallel. In at least one embodiment, cooperating threads can refer to aplurality of threads including instructions to perform task and thatexchange data through shared memory. In at least one embodiment, threadsand cooperating threads are described in more detail, in accordance withat least one embodiment, in conjunction with FIG. 39 . In at least oneembodiment, at least one component shown or described with respect toFIG. 37 is used to implement techniques and/or functions described inconnection with FIGS. 1-15B.

FIG. 38 illustrates a general processing cluster (“GPC”) 3800, accordingto at least one embodiment. In at least one embodiment, GPC 3800 is GPC3718 of FIG. 37 . In at least one embodiment, each GPC 3800 includes,without limitation, a number of hardware units for processing tasks andeach GPC 3800 includes, without limitation, a pipeline manager 3802, apre-raster operations unit (“PROP”) 3804, a raster engine 3808, a workdistribution crossbar (“WDX”) 3816, a memory management unit (“MMU”)3818, one or more Data Processing Clusters (“DPCs”) 3806, and anysuitable combination of parts.

In at least one embodiment, operation of GPC 3800 is controlled bypipeline manager 3802. In at least one embodiment, pipeline manager 3802manages configuration of one or more DPCs 3806 for processing tasksallocated to GPC 3800. In at least one embodiment, pipeline manager 3802configures at least one of one or more DPCs 3806 to implement at least aportion of a graphics rendering pipeline. In at least one embodiment,DPC 3806 is configured to execute a vertex shader program on aprogrammable streaming multi-processor (“SM”) 3814. In at least oneembodiment, pipeline manager 3802 is configured to route packetsreceived from a work distribution unit to appropriate logical unitswithin GPC 3800, in at least one embodiment, and some packets may berouted to fixed function hardware units in PROP 3804 and/or rasterengine 3808 while other packets may be routed to DPCs 3806 forprocessing by a primitive engine 3812 or SM 3814. In at least oneembodiment, pipeline manager 3802 configures at least one of DPCs 3806to implement a neural network model and/or a computing pipeline.

In at least one embodiment, PROP unit 3804 is configured, in at leastone embodiment, to route data generated by raster engine 3808 and DPCs3806 to a Raster Operations (“ROP”) unit in partition unit 3722,described in more detail above in conjunction with FIG. 37 . In at leastone embodiment, PROP unit 3804 is configured to perform optimizationsfor color blending, organize pixel data, perform address translations,and more. In at least one embodiment, raster engine 3808 includes,without limitation, a number of fixed function hardware units configuredto perform various raster operations, in at least one embodiment, andraster engine 3808 includes, without limitation, a setup engine, acoarse raster engine, a culling engine, a clipping engine, a fine rasterengine, a tile coalescing engine, and any suitable combination thereof.In at least one embodiment, setup engine receives transformed verticesand generates plane equations associated with geometric primitivedefined by vertices; plane equations are transmitted to coarse rasterengine to generate coverage information (e.g., an x, y coverage mask fora tile) for primitive; output of coarse raster engine is transmitted toculling engine where fragments associated with primitive that fail az-test are culled, and transmitted to a clipping engine where fragmentslying outside a viewing frustum are clipped. In at least one embodiment,fragments that survive clipping and culling are passed to fine rasterengine to generate attributes for pixel fragments based on planeequations generated by setup engine. In at least one embodiment, outputof raster engine 3808 comprises fragments to be processed by anysuitable entity such as by a fragment shader implemented within DPC3806.

In at least one embodiment, each DPC 3806 included in GPC 3800 comprise,without limitation, an M-Pipe Controller (“MPC”) 3810; primitive engine3812; one or more SMs 3814; and any suitable combination thereof. In atleast one embodiment, MPC 3810 controls operation of DPC 3806, routingpackets received from pipeline manager 3802 to appropriate units in DPC3806. In at least one embodiment, packets associated with a vertex arerouted to primitive engine 3812, which is configured to fetch vertexattributes associated with vertex from memory; in contrast, packetsassociated with a shader program may be transmitted to SM 3814.

In at least one embodiment, SM 3814 comprises, without limitation, aprogrammable streaming processor that is configured to process tasksrepresented by a number of threads. In at least one embodiment, SM 3814is multi-threaded and configured to execute a plurality of threads(e.g., 32 threads) from a particular group of threads concurrently andimplements a Single-Instruction, Multiple-Data (“SIMD”) architecturewhere each thread in a group of threads (e.g., a warp) is configured toprocess a different set of data based on same set of instructions. In atleast one embodiment, all threads in group of threads execute sameinstructions. In at least one embodiment, SM 3814 implements aSingle-Instruction, Multiple Thread (“SIMT”) architecture wherein eachthread in a group of threads is configured to process a different set ofdata based on same set of instructions, but where individual threads ingroup of threads are allowed to diverge during execution. In at leastone embodiment, a program counter, call stack, and execution state ismaintained for each warp, enabling concurrency between warps and serialexecution within warps when threads within warp diverge. In anotherembodiment, a program counter, call stack, and execution state ismaintained for each individual thread, enabling equal concurrencybetween all threads, within and between warps. In at least oneembodiment, execution state is maintained for each individual thread andthreads executing same instructions may be converged and executed inparallel for better efficiency. At least one embodiment of SM 3814 aredescribed in more detail herein.

In at least one embodiment, MMU 3818 provides an interface between GPC3800 and memory partition unit (e.g., partition unit 3722 of FIG. 37 )and MMU 3818 provides translation of virtual addresses into physicaladdresses, memory protection, and arbitration of memory requests. In atleast one embodiment, MMU 3818 provides one or more translationlookaside buffers (“TLBs”) for performing translation of virtualaddresses into physical addresses in memory. In at least one embodiment,at least one component shown or described with respect to FIG. 38 isused to implement techniques and/or functions described in connectionwith FIGS. 1-15B.

FIG. 39 illustrates a memory partition unit 3900 of a parallelprocessing unit (“PPU”), in accordance with at least one embodiment. Inat least one embodiment, memory partition unit 3900 includes, withoutlimitation, a Raster Operations (“ROP”) unit 3902; a level two (“L2”)cache 3904; a memory interface 3906; and any suitable combinationthereof. In at least one embodiment, memory interface 3906 is coupled tomemory. In at least one embodiment, memory interface 3906 may implement32, 64, 128, 1024-bit data buses, or like, for high-speed data transfer.In at least one embodiment, PPU incorporates U memory interfaces 3906,one memory interface 3906 per pair of partition units 3900, where eachpair of partition units 3900 is connected to a corresponding memorydevice. For example, in at least one embodiment, PPU may be connected toup to Y memory devices, such as high bandwidth memory stacks or graphicsdouble-data-rate, version 5, synchronous dynamic random access memory(“GDDR5 SDRAM”).

In at least one embodiment, memory interface 3906 implements a highbandwidth memory second generation (“HBM2”) memory interface and Yequals half U. In at least one embodiment, HBM2 memory stacks arelocated on same physical package as PPU, providing substantial power andarea savings compared with conventional GDDR5 SDRAM systems. In at leastone embodiment, each HBM2 stack includes, without limitation, fourmemory dies and Y equals 4, with each HBM2 stack including two 128-bitchannels per die for a total of 8 channels and a data bus width of 1024bits. In at least one embodiment, memory supports Single-ErrorCorrecting Double-Error Detecting (“SECDED”) Error Correction Code(“ECC”) to protect data. ECC provides higher reliability for computeapplications that are sensitive to data corruption.

In at least one embodiment, PPU implements a multi-level memoryhierarchy. In at least one embodiment, memory partition unit 3900supports a unified memory to provide a single unified virtual addressspace for central processing unit (“CPU”) and PPU memory, enabling datasharing between virtual memory systems. In at least one embodimentfrequency of accesses by a PPU to memory located on other processors istraced to ensure that memory pages are moved to physical memory of PPUthat is accessing pages more frequently. In at least one embodiment,high-speed GPU interconnect 3708 supports address translation servicesallowing PPU to directly access a CPU's page tables and providing fullaccess to CPU memory by PPU.

In at least one embodiment, copy engines transfer data between multiplePPUs or between PPUs and CPUs. In at least one embodiment, copy enginescan generate page faults for addresses that are not mapped into pagetables and memory partition unit 3900 then services page faults, mappingaddresses into page table, after which copy engine performs transfer. Inat least one embodiment, memory is pinned (i.e., non-pageable) formultiple copy engine operations between multiple processors,substantially reducing available memory. In at least one embodiment,with hardware page faulting, addresses can be passed to copy engineswithout regard as to whether memory pages are resident, and copy processis transparent.

Data from memory 3704 of FIG. 37 or other system memory is fetched bymemory partition unit 3900 and stored in L2 cache 3904, which is locatedon-chip and is shared between various GPCs, in accordance with at leastone embodiment. Each memory partition unit 3900, in at least oneembodiment, includes, without limitation, at least a portion of L2 cacheassociated with a corresponding memory device. In at least oneembodiment, lower level caches are implemented in various units withinGPCs. In at least one embodiment, each of SMs 3814 may implement a levelone (“L1”) cache wherein L1 cache is private memory that is dedicated toa particular SM 3814 and data from L2 cache 3904 is fetched and storedin each of L1 caches for processing in functional units of SMs 3814. Inat least one embodiment, L2 cache 3904 is coupled to memory interface3906 and XBar 3720.

ROP unit 3902 performs graphics raster operations related to pixelcolor, such as color compression, pixel blending, and more, in at leastone embodiment. ROP unit 3902, in at least one embodiment, implementsdepth testing in conjunction with raster engine 3808, receiving a depthfor a sample location associated with a pixel fragment from cullingengine of raster engine 3808. In at least one embodiment, depth istested against a corresponding depth in a depth buffer for a samplelocation associated with fragment. In at least one embodiment, iffragment passes depth test for sample location, then ROP unit 3902updates depth buffer and transmits a result of depth test to rasterengine 3808. It will be appreciated that number of partition units 3900may be different than number of GPCs and, therefore, each ROP unit 3902can, in at least one embodiment, be coupled to each of GPCs. In at leastone embodiment, ROP unit 3902 tracks packets received from differentGPCs and determines which that a result generated by ROP unit 3902 isrouted to through XBar 3720.

FIG. 40 illustrates a streaming multi-processor (“SM”) 4000, accordingto at least one embodiment. In at least one embodiment, SM 4000 is SM ofFIG. 38 . In at least one embodiment, SM 4000 includes, withoutlimitation, an instruction cache 4002; one or more scheduler units 4004;a register file 4008; one or more processing cores (“cores”) 4010; oneor more special function units (“SFUs”) 4012; one or more load/storeunits (“LSUs”) 4014; an interconnect network 4016; a shared memory/levelone (“L1”) cache 4018; and any suitable combination thereof. In at leastone embodiment, a work distribution unit dispatches tasks for executionon general processing clusters (“GPCs”) of parallel processing units(“PPUs”) and each task is allocated to a particular Data ProcessingCluster (“DPC”) within a GPC and, if task is associated with a shaderprogram, task is allocated to one of SMs 4000. In at least oneembodiment, scheduler unit 4004 receives tasks from work distributionunit and manages instruction scheduling for one or more thread blocksassigned to SM 4000. In at least one embodiment, scheduler unit 4004schedules thread blocks for execution as warps of parallel threads,wherein each thread block is allocated at least one warp. In at leastone embodiment, each warp executes threads. In at least one embodiment,scheduler unit 4004 manages a plurality of different thread blocks,allocating warps to different thread blocks and then dispatchinginstructions from plurality of different cooperative groups to variousfunctional units (e.g., processing cores 4010, SFUs 4012, and LSUs 4014)during each clock cycle.

In at least one embodiment, Cooperative Groups may refer to aprogramming model for organizing groups of communicating threads thatallows developers to express granularity at which threads arecommunicating, enabling expression of richer, more efficient paralleldecompositions. In at least one embodiment, cooperative launch APIssupport synchronization amongst thread blocks for execution of parallelalgorithms. In at least one embodiment, applications of conventionalprogramming models provide a single, simple construct for synchronizingcooperating threads: a barrier across all threads of a thread block(e.g., syncthreads( ) function). However, in at least one embodiment,programmers may define groups of threads at smaller than thread blockgranularities and synchronize within defined groups to enable greaterperformance, design flexibility, and software reuse in form ofcollective group-wide function interfaces. In at least one embodiment,Cooperative Groups enables programmers to define groups of threadsexplicitly at sub-block (i.e., as small as a single thread) andmulti-block granularities, and to perform collective operations such assynchronization on threads in a cooperative group. In at least oneembodiment, programming model supports clean composition across softwareboundaries, so that libraries and utility functions can synchronizesafely within their local context without having to make assumptionsabout convergence. In at least one embodiment, Cooperative Groupsprimitives enable new patterns of cooperative parallelism, including,without limitation, producer-consumer parallelism, opportunisticparallelism, and global synchronization across an entire grid of threadblocks.

In at least one embodiment, a dispatch unit 4006 is configured totransmit instructions to one or more of functional units and schedulerunit 4004 includes, without limitation, two dispatch units 4006 thatenable two different instructions from same warp to be dispatched duringeach clock cycle. In at least one embodiment, each scheduler unit 4004includes a single dispatch unit 4006 or additional dispatch units 4006.

In at least one embodiment, each SM 4000, in at least one embodiment,includes, without limitation, register file 4008 that provides a set ofregisters for functional units of SM 4000. In at least one embodiment,register file 4008 is divided between each of functional units such thateach functional unit is allocated a dedicated portion of register file4008. In at least one embodiment, register file 4008 is divided betweendifferent warps being executed by SM 4000 and register file 4008provides temporary storage for operands connected to data paths offunctional units. In at least one embodiment, each SM 4000 comprises,without limitation, a plurality of L processing cores 4010. In at leastone embodiment, SM 4000 includes, without limitation, a large number(e.g., 128 or more) of distinct processing cores 4010. In at least oneembodiment, each processing core 4010, in at least one embodiment,includes, without limitation, a fully-pipelined, single-precision,double-precision, and/or mixed precision processing unit that includes,without limitation, a floating point arithmetic logic unit and aninteger arithmetic logic unit. In at least one embodiment, floatingpoint arithmetic logic units implement IEEE 754-2008 standard forfloating point arithmetic. In at least one embodiment, processing cores4010 include, without limitation, 64 single-precision (32-bit) floatingpoint cores, 64 integer cores, 32 double-precision (64-bit) floatingpoint cores, and 8 tensor cores.

Tensor cores are configured to perform matrix operations in accordancewith at least one embodiment. In at least one embodiment, one or moretensor cores are included in processing cores 4010. In at least oneembodiment, tensor cores are configured to perform deep learning matrixarithmetic, such as convolution operations for neural network trainingand inferencing. In at least one embodiment, each tensor core operateson a 4×4 matrix and performs a matrix multiply and accumulate operationD=A×B+C, where A, B, C, and D are 4×4 matrices.

In at least one embodiment, matrix multiply inputs A and B are 16-bitfloating point matrices and accumulation matrices C and D are 16-bitfloating point or 32-bit floating point matrices. In at least oneembodiment, tensor cores operate on 16-bit floating point input datawith 32-bit floating point accumulation. In at least one embodiment,16-bit floating point multiply uses 64 operations and results in a fullprecision product that is then accumulated using 32-bit floating pointaddition with other intermediate products for a 4×4×4 matrix multiply.Tensor cores are used to perform much larger two-dimensional or higherdimensional matrix operations, built up from these smaller elements, inat least one embodiment. In at least one embodiment, an API, such asCUDA 9 C++ API, exposes specialized matrix load, matrix multiply andaccumulate, and matrix store operations to efficiently use tensor coresfrom a CUDA-C++ program. In at least one embodiment, at CUDA level,warp-level interface assumes 16×16 size matrices spanning all 32 threadsof warp.

In at least one embodiment, each SM 4000 comprises, without limitation,M SFUs 4012 that perform special functions (e.g., attribute evaluation,reciprocal square root, and like). In at least one embodiment, SFUs 4012include, without limitation, a tree traversal unit configured totraverse a hierarchical tree data structure. In at least one embodiment,SFUs 4012 include, without limitation, a texture unit configured toperform texture map filtering operations. In at least one embodiment,texture units are configured to load texture maps (e.g., a 2D array oftexels) from memory and sample texture maps to produce sampled texturevalues for use in shader programs executed by SM 4000. In at least oneembodiment, texture maps are stored in shared memory/L1 cache 4018. Inat least one embodiment, texture units implement texture operations suchas filtering operations using mip-maps (e.g., texture maps of varyinglevels of detail), in accordance with at least one embodiment. In atleast one embodiment, each SM 4000 includes, without limitation, twotexture units.

Each SM 4000 comprises, without limitation, N LSUs 4014 that implementload and store operations between shared memory/L1 cache 4018 andregister file 4008, in at least one embodiment. Each SM 4000 includes,without limitation, interconnect network 4016 that connects each offunctional units to register file 4008 and LSU 4014 to register file4008 and shared memory/L1 cache 4018 in at least one embodiment. In atleast one embodiment, interconnect network 4016 is a crossbar that canbe configured to connect any of functional units to any of registers inregister file 4008 and connect LSUs 4014 to register file 4008 andmemory locations in shared memory/L1 cache 4018.

In at least one embodiment, shared memory/L1 cache 4018 is an array ofon-chip memory that allows for data storage and communication between SM4000 and primitive engine and between threads in SM 4000, in at leastone embodiment. In at least one embodiment, shared memory/L1 cache 4018comprises, without limitation, 128 KB of storage capacity and is in pathfrom SM 4000 to partition unit. In at least one embodiment, sharedmemory/L1 cache 4018, in at least one embodiment, is used to cache readsand writes. In at least one embodiment, one or more of shared memory/L1cache 4018, L2 cache, and memory are backing stores.

Combining data cache and shared memory functionality into a singlememory block provides improved performance for both types of memoryaccesses, in at least one embodiment. In at least one embodiment,capacity is used or is usable as a cache by programs that do not useshared memory, such as if shared memory is configured to use half ofcapacity, texture and load/store operations can use remaining capacity.Integration within shared memory/L1 cache 4018 enables shared memory/L1cache 4018 to function as a high-throughput conduit for streaming datawhile simultaneously providing high-bandwidth and low-latency access tofrequently reused data, in accordance with at least one embodiment. Inat least one embodiment, when configured for general purpose parallelcomputation, a simpler configuration can be used compared with graphicsprocessing. In at least one embodiment, fixed function graphicsprocessing units are bypassed, creating a much simpler programmingmodel. In general purpose parallel computation configuration, workdistribution unit assigns and distributes blocks of threads directly toDPCs, in at least one embodiment. In at least one embodiment, threads ina block execute same program, using a unique thread ID in calculation toensure each thread generates unique results, using SM 4000 to executeprogram and perform calculations, shared memory/L1 cache 4018 tocommunicate between threads, and LSU 4014 to read and write globalmemory through shared memory/L1 cache 4018 and memory partition unit. Inat least one embodiment, when configured for general purpose parallelcomputation, SM 4000 writes commands that scheduler unit 4004 can use tolaunch new work on DPCs.

In at least one embodiment, PPU is included in or coupled to a desktopcomputer, a laptop computer, a tablet computer, servers, supercomputers,a smart-phone (e.g., a wireless, hand-held device), personal digitalassistant (“PDA”), a digital camera, a vehicle, a head mounted display,a hand-held electronic device, and more. In at least one embodiment, PPUis embodied on a single semiconductor substrate. In at least oneembodiment, PPU is included in a system-on-a-chip (“SoC”) along with oneor more other devices such as additional PPUs, memory, a reducedinstruction set computer (“RISC”) CPU, a memory management unit (“MMU”),a digital-to-analog converter (“DAC”), and like.

In at least one embodiment, PPU may be included on a graphics card thatincludes one or more memory devices. In at least one embodiment,graphics card may be configured to interface with a PCIe slot on amotherboard of a desktop computer. In at least one embodiment, PPU maybe an integrated graphics processing unit (“iGPU”) included in chipsetof motherboard In at least one embodiment, at least one component shownor described with respect to FIG. 39 is used to implement techniquesand/or functions described in connection with FIGS. 1-15B.

In at least one embodiment, a single semiconductor platform may refer toa sole unitary semiconductor-based integrated circuit or chip. In atleast one embodiment, multi-chip modules may be used with increasedconnectivity which simulate on-chip operation, and make substantialimprovements over utilizing a conventional central processing unit(“CPU”) and bus implementation. In at least one embodiment, variousmodules may also be situated separately or in various combinations ofsemiconductor platforms per desires of user.

In at least one embodiment, computer programs in form ofmachine-readable executable code or computer control logic algorithmsare stored in main memory 2004 and/or secondary storage. Computerprograms, if executed by one or more processors, enable system 2000 toperform various functions in accordance with at least one embodiment. Inat least one embodiment, memory 2004, storage, and/or any other storageare possible examples of computer-readable media. In at least oneembodiment, secondary storage may refer to any suitable storage deviceor system such as a hard disk drive and/or a removable storage drive,representing a floppy disk drive, a magnetic tape drive, a compact diskdrive, digital versatile disk (“DVD”) drive, recording device, universalserial bus (“USB”) flash memory, etc. In at least one embodiment,architecture and/or functionality of various previous figures areimplemented in context of CPU 2002; parallel processing system 2012; anintegrated circuit capable of at least a portion of capabilities of bothCPU 2002; parallel processing system 2012; a chipset (e.g., a group ofintegrated circuits designed to work and sold as a unit for performingrelated functions, etc.); and any suitable combination of integratedcircuit(s).

In at least one embodiment, architecture and/or functionality of variousprevious figures are implemented in context of a general computersystem, a circuit board system, a game console system dedicated forentertainment purposes, an application-specific system, and more. In atleast one embodiment, computer system 2000 may take form of a desktopcomputer, a laptop computer, a tablet computer, servers, supercomputers,a smart-phone (e.g., a wireless, hand-held device), personal digitalassistant (“PDA”), a digital camera, a vehicle, a head mounted display,a hand-held electronic device, a mobile phone device, a television,workstation, game consoles, embedded system, and/or any other type oflogic.

In at least one embodiment, parallel processing system 2012 includes,without limitation, a plurality of parallel processing units (“PPUs”)2014 and associated memories 2016. In at least one embodiment, PPUs 2014are connected to a host processor or other peripheral devices via aninterconnect 2018 and a switch 2020 or multiplexer. In at least oneembodiment, parallel processing system 2012 distributes computationaltasks across PPUs 2014 which can be parallelizable—for example, as partof distribution of computational tasks across multiple graphicsprocessing unit (“GPU”) thread blocks. In at least one embodiment,memory is shared and accessible (e.g., for read and/or write access)across some or all of PPUs 2014, although such shared memory may incurperformance penalties relative to use of local memory and registersresident to a PPU 2014. In at least one embodiment, operation of PPUs2014 is synchronized through use of a command such as syncthreads( ),wherein all threads in a block (e.g., executed across multiple PPUs2014) to reach a certain point of execution of code before proceeding.

Networks

FIG. 41 illustrates a network 4100 for communicating data within a 5Gwireless communications network, in accordance with at least oneembodiment. In at least one embodiment, network 4100 comprises a basestation 4106 having a coverage area 4104, a plurality of mobile devices4108, and a backhaul network 4102. In at least one embodiment, as shown,base station 4106 establishes uplink and/or downlink connections withmobile devices 4108, which serve to carry data from mobile devices 4108to base station 4106 and vice-versa. In at least one embodiment, datacarried over uplink/downlink connections may include data communicatedbetween mobile devices 4108, as well as data communicated to/from aremote-end (not shown) by way of backhaul network 4102. In at least oneembodiment, term “base station” refers to any component (or collectionof components) configured to provide wireless access to a network, suchas an enhanced base station (eNB), a macro-cell, a femtocell, a Wi-Fiaccess point (AP), or other wirelessly enabled devices. In at least oneembodiment, base stations may provide wireless access in accordance withone or more wireless communication protocols, e.g., long term evolution(LTE), LTE advanced (LTE-A), High Speed Packet Access (HSPA), Wi-Fi802.11a/b/g/n/ac, etc. In at least one embodiment, term “mobile device”refers to any component (or collection of components) capable ofestablishing a wireless connection with a base station, such as a userequipment (UE), a mobile station (STA), and other wirelessly enableddevices. In some embodiments, network 4100 may comprise various otherwireless devices, such as relays, low power nodes, etc. In at least oneembodiment, at least one component shown or described with respect toFIG. 41 is used to implement techniques and/or functions described inconnection with FIGS. 1-15B.

FIG. 42 illustrates a network architecture 4200 for a 5G wirelessnetwork, in accordance with at least one embodiment. In at least oneembodiment, as shown, network architecture 4200 includes a radio accessnetwork (RAN) 4204, an evolved packet core (EPC) 4202, which may bereferred to as a core network, and a home network 4216 of a UE 4208attempting to access RAN 4204. In at least one embodiment, RAN 4204 andEPC 4202 form a serving wireless network. In at least one embodiment,RAN 4204 includes a base station 4206, and EPC 4202 includes a mobilitymanagement entity (MME) 4212, a serving gateway (SGW) 4210, and a packetdata network (PDN) gateway (PGW) 4214. In at least one embodiment, homenetwork 4216 includes an application server 4218 and a home subscriberserver (HSS) 4220. In at least one embodiment, HSS 4220 may be part ofhome network 4216, EPC 4202, and/or variations thereof.

In at least one embodiment, MME 4212 is a termination point in a networkfor ciphering/integrity protection for NAS signaling and handlessecurity key management. In at least one embodiment, it should beappreciated that term “MME” is used in 4G LTE networks, and that 5G LTEnetworks may include a Security Anchor Node (SEAN) or a Security AccessFunction (SEAF) that performs similar functions. In at least oneembodiment, terms “MME,” “SEAN,” and “SEAF” may be used interchangeably.In at least one embodiment, MME 4212 also provides control planefunction for mobility between LTE and 2G/3G access networks, as well asan interface to home networks of roaming UEs. In at least oneembodiment, SGW 4210 routes and forwards user data packets, while alsoacting as a mobility anchor for a user plane during handovers. In atleast one embodiment, PGW 4214 provides connectivity from UEs toexternal packet data networks by being a point of exit and entry oftraffic for UEs. In at least one embodiment, HSS 4220 is a centraldatabase that contains user-related and subscription-relatedinformation. In at least one embodiment, application server 4218 is acentral database that contains user-related information regardingvarious applications that may utilize and communicate via networkarchitecture 4200. In at least one embodiment, at least one componentshown or described with respect to FIG. 42 is used to implementtechniques and/or functions described in connection with FIGS. 1-15B.

FIG. 43 is a diagram illustrating some basic functionality of a mobiletelecommunications network/system operating in accordance with LTE and5G principles, in accordance with at least one embodiment. In at leastone embodiment, a mobile telecommunications system includesinfrastructure equipment comprising base stations 4314 which areconnected to a core network 4302, which operates in accordance with aconventional arrangement which will be understood by those acquaintedwith communications technology. In at least one embodiment,infrastructure equipment 4314 may also be referred to as a base station,network element, enhanced NodeB (eNodeB) or a coordinating entity forexample, and provides a wireless access interface to one or morecommunications devices within a coverage area or cell represented by abroken line 4304, which may be referred to as a radio access network. Inat least one embodiment, one or more mobile communications devices 4306may communicate data via transmission and reception of signalsrepresenting data using a wireless access interface. In at least oneembodiment, core network 4302 may also provide functionality includingauthentication, mobility management, charging and so on forcommunications devices served by a network entity.

In at least one embodiment, mobile communications devices of FIG. 43 mayalso be referred to as communications terminals, user equipment (UE),terminal devices and so forth, and are configured to communicate withone or more other communications devices served by a same or a differentcoverage area via a network entity. In at least one embodiment, thesecommunications may be performed by transmitting and receiving signalsrepresenting data using a wireless access interface over two waycommunications links.

In at least one embodiment, as shown in FIG. 43 , one of eNodeBs 4314 ais shown in more detail to include a transmitter 4312 for transmittingsignals via a wireless access interface to one or more communicationsdevices or UEs 4306, and a receiver 4310 to receive signals from one ormore UEs within coverage area 4304. In at least one embodiment,controller 4308 controls transmitter 4312 and receiver 4310 to transmitand receive signals via a wireless access interface. In at least oneembodiment, controller 4308 may perform a function of controllingallocation of communications resource elements of a wireless accessinterface and may in some examples include a scheduler for schedulingtransmissions via a wireless access interface for both uplink anddownlink.

In at least one embodiment, an example UE 4306 a is shown in more detailto include a transmitter 4320 for transmitting signals on an uplink of awireless access interface to eNodeB 4314 and a receiver 4318 forreceiving signals transmitted by eNodeB 4314 on a downlink via awireless access interface. In at least one embodiment, transmitter 4320and receiver 4318 are controlled by a controller 4316. In at least oneembodiment, at least one component shown or described with respect toFIG. 43 is used to implement techniques and/or functions described inconnection with FIGS. 1-15B.

FIG. 44 illustrates a radio access network 4400, which may be part of a5G network architecture, in accordance with at least one embodiment. Inat least one embodiment, radio access network 4400 covers a geographicregion divided into a number of cellular regions (cells) that can beuniquely identified by a user equipment (UE) based on an identificationbroadcasted over a geographical area from one access point or basestation. In at least one embodiment, macrocells 4440, 4428, and 4416,and a small cell 4430, may include one or more sectors. In at least oneembodiment, a sector is a sub-area of a cell and all sectors within onecell are served by a same base station. In at least one embodiment, asingle logical identification belonging to that sector can identify aradio link within a sector. In at least one embodiment, multiple sectorswithin a cell can be formed by groups of antennas with each antennaresponsible for communication with UEs in a portion of a cell.

In at least one embodiment, each cell is served by a base station (BS).In at least one embodiment, a base station is a network element in aradio access network responsible for radio transmission and reception inone or more cells to or from a UE. In at least one embodiment, a basestation may also be referred to as a base transceiver station (BTS), aradio base station, a radio transceiver, a transceiver function, a basicservice set (BSS), an extended service set (ESS), an access point (AP),a Node B (NB), an eNode B (eNB), a gNode B (gNB), or some other suitableterminology. In at least one embodiment, base stations may include abackhaul interface for communication with a backhaul portion of anetwork. In at least one embodiment, a base station has an integratedantenna or is connected to an antenna or remote radio head (RRH) byfeeder cables.

In at least one embodiment, a backhaul may provide a link between a basestation and a core network, and in some examples, a backhaul may provideinterconnection between respective base stations. In at least oneembodiment, a core network is a part of a wireless communication systemthat is generally independent of radio access technology used in a radioaccess network. In at least one embodiment, various types of backhaulinterfaces, such as a direct physical connection, a virtual network, orlike using any suitable transport network, may be employed. In at leastone embodiment, some base stations may be configured as integratedaccess and backhaul (IAB) nodes, where a wireless spectrum may be usedboth for access links (i.e., wireless links with UEs), and for backhaullinks, which is sometimes referred to as wireless self-backhauling. Inat least one embodiment, through wireless self-backhauling, a wirelessspectrum utilized for communication between a base station and UE may beleveraged for backhaul communication, enabling fast and easy deploymentof highly dense small cell networks, as opposed to requiring each newbase station deployment to be outfitted with its own hard-wired backhaulconnection.

In at least one embodiment, high-power base stations 4436 and 4420 areshown in cells 4440 and 4428, and a high-power base station 4410 isshown controlling a remote radio head (RRH) 4412 in cell 4416. In atleast one embodiment, cells 4440, 4428, and 4416 may be referred to aslarge size cells or macrocells. In at least one embodiment, a low-powerbase station 4434 is shown in small cell 4430 (e.g., a microcell,picocell, femtocell, home base station, home Node B, home eNode B, etc.)which may overlap with one or more macrocells, and may be referred to asa small cell or small size cell. In at least one embodiment, cell sizingcan be done according to system design as well as component constraints.In at least one embodiment, a relay node may be deployed to extend sizeor coverage area of a given cell. In at least one embodiment, radioaccess network 4400 may include any number of wireless base stations andcells. In at least one embodiment, base stations 4436, 4420, 4410, 4434provide wireless access points to a core network for any number ofmobile apparatuses.

In at least one embodiment, a quadcopter or drone 4442 may be configuredto function as a base station. In at least one embodiment, a cell maynot necessarily be stationary, and a geographic area of a cell may moveaccording to a location of a mobile base station such as quadcopter4442.

In at least one embodiment, radio access network 4400 supports wirelesscommunications for multiple mobile apparatuses. In at least oneembodiment, a mobile apparatus is commonly referred to as user equipment(UE), but may also be referred to as a mobile station (MS), a subscriberstation, a mobile unit, a subscriber unit, a wireless unit, a remoteunit, a mobile device, a wireless device, a wireless communicationsdevice, a remote device, a mobile subscriber station, an access terminal(AT), a mobile terminal, a wireless terminal, a remote terminal, ahandset, a terminal, a user agent, a mobile client, a client, or someother suitable terminology. In at least one embodiment, a UE may be anapparatus that provides a user with access to network services.

In at least one embodiment, a “mobile” apparatus need not necessarilyhave a capability to move and may be stationary. In at least oneembodiment, mobile apparatus or mobile device broadly refers to adiverse array of devices and technologies. In at least one embodiment, amobile apparatus may be a mobile, a cellular (cell) phone, a smartphone, a session initiation protocol (SIP) phone, a laptop, a personalcomputer (PC), a notebook, a netbook, a smartbook, a tablet, a personaldigital assistant (PDA), a broad array of embedded systems, e.g.,corresponding to an “Internet of things” (IoT), an automotive or othertransportation vehicle, a remote sensor or actuator, a robot or roboticsdevice, a satellite radio, a global positioning system (GPS) device, anobject tracking device, a drone, a multi-copter, a quad-copter, a remotecontrol device, a consumer and/or wearable device, such as eyewear, awearable camera, a virtual reality device, a smart watch, a health orfitness tracker, a digital audio player (e.g., MP3 player), a camera, agame console, a digital home or smart home device such as a home audio,video, and/or multimedia device, an appliance, a vending machine,intelligent lighting, a home security system, a smart meter, a securitydevice, a solar panel or solar array, a municipal infrastructure devicecontrolling electric power (e.g., a smart grid), lighting, water, etc.,an industrial automation and enterprise device, a logistics controller,agricultural equipment, military defense equipment, vehicles, aircraft,ships, and weaponry, etc. In at least one embodiment, a mobile apparatusmay provide for connected medicine or telemedicine support, i.e., healthcare at a distance. In at least one embodiment, telehealth devices mayinclude telehealth monitoring devices and telehealth administrationdevices, whose communication may be given preferential treatment orprioritized access over other types of information, e.g., in terms ofprioritized access for transport of critical service data, and/orrelevant QoS for transport of critical service data.

In at least one embodiment, cells of radio access network 4400 mayinclude UEs that may be in communication with one or more sectors ofeach cell. In at least one embodiment, UEs 4414 and 4408 may be incommunication with base station 4410 by way of RRH 4412; UEs 4422 and4426 may be in communication with base station 4420; UE 4432 may be incommunication with low-power base station 4434; UEs 4438 and 4418 may bein communication with base station 4436; and UE 4444 may be incommunication with mobile base station 4442. In at least one embodiment,each base station 4410, 4420, 4434, 4436, and 4442 may be configured toprovide an access point to a core network (not shown) for all UEs inrespective cells and transmissions from a base station (e.g., basestation 4436) to one or more UEs (e.g., UEs 4438 and 4418) may bereferred to as downlink (DL) transmission, while transmissions from a UE(e.g., UE 4438) to a base station may be referred to as uplink (UL)transmissions. In at least one embodiment, downlink may refer to apoint-to-multipoint transmission, which may be referred to as broadcastchannel multiplexing. In at least one embodiment, uplink may refer to apoint-to-point transmission.

In at least one embodiment, quadcopter 4442, which may be referred to asa mobile network node, may be configured to function as a UE within cell4440 by communicating with base station 4436. In at least oneembodiment, multiple UEs (e.g., UEs 4422 and 4426) may communicate witheach other using peer to peer (P2P) or sidelink signals 4424, which maybypass a base station such as base station 4420.

In at least one embodiment, ability for a UE to communicate whilemoving, independent of its location, is referred to as mobility. In atleast one embodiment, a mobility management entity (MME) sets up,maintains, and releases various physical channels between a UE and aradio access network. In at least one embodiment, DL-based mobility orUL-based mobility may be utilized by a radio access network 4400 toenable mobility and handovers (i.e., transfer of a UE's connection fromone radio channel to another). In at least one embodiment, a UE, in anetwork configured for DL-based mobility, may monitor various parametersof a signal from its serving cell as well as various parameters ofneighboring cells, and, depending on a quality of these parameters, a UEmay maintain communication with one or more neighboring cells. In atleast one embodiment, if signal quality from a neighboring cell exceedsthat from a serving cell for a given amount of time, or if a UE movesfrom one cell to another, a UE may undertake a handoff or handover froma serving cell to a neighboring (target) cell. In at least oneembodiment, UE 4418 (illustrated as a vehicle, although any suitableform of UE may be used) may move from a geographic area corresponding toa cell, such as serving cell 4440, to a geographic area corresponding toa neighbor cell, such as neighbor cell 4416. In at least one embodiment,UE 4418 may transmit a reporting message to its serving base station4436 indicating its condition when signal strength or quality from aneighbor cell 4416 exceeds that of its serving cell 4440 for a givenamount of time. In at least one embodiment, UE 4418 may receive ahandover command, and may undergo a handover to cell 4416.

In at least one embodiment, UL reference signals from each UE may beutilized by a network configured for UL-based mobility to select aserving cell for each UE. In at least one embodiment, base stations4436, 4420, and 4410/4412 may broadcast unified synchronization signals(e.g., unified Primary Synchronization Signals (PSSs), unified SecondarySynchronization Signals (SSSs) and unified Physical Broadcast Channels(PBCH)). In at least one embodiment, UEs 4438, 4418, 4422, 4426, 4414,and 4408 may receive unified synchronization signals, derive a carrierfrequency and slot timing from synchronization signals, and in responseto deriving timing, transmit an uplink pilot or reference signal. In atleast one embodiment, two or more cells (e.g., base stations 4436 and4410/4412) within radio access network 4400 may concurrently receive anuplink pilot signal transmitted by a UE (e.g., UE 4418). In at least oneembodiment, cells may measure a strength of a pilot signal, and a radioaccess network (e.g., one or more of base stations 4436 and 4410/4412and/or a central node within a core network) may determine a servingcell for UE 4418. In at least one embodiment, a network may continue tomonitor an uplink pilot signal transmitted by UE 4418 as UE 4418 movesthrough radio access network 4400. In at least one embodiment, a network4400 may handover UE 4418 from a serving cell to a neighboring cell,with or without informing UE 4418, when a signal strength or quality ofa pilot signal measured by a neighboring cell exceeds that of a signalstrength or quality measured by a serving cell.

In at least one embodiment, synchronization signals transmitted by basestations 4436, 4420, and 4410/4412 may be unified, but may not identifya particular cell and rather may identify a zone of multiple cellsoperating on a same frequency and/or with a same timing. In at least oneembodiment, zones in 5G networks or other next generation communicationnetworks enable uplink-based mobility framework and improves efficiencyof both a UE and a network, since amounts of mobility messages that needto be exchanged between a UE and a network may be reduced.

In at least one embodiment, air interface in a radio access network 4400may utilize unlicensed spectrum, licensed spectrum, or shared spectrum.In at least one embodiment, unlicensed spectrum provides for shared useof a portion of a spectrum without need for a government-grantedlicense, however, while compliance with some technical rules isgenerally still required to access an unlicensed spectrum, generally,any operator or device may gain access. In at least one embodiment,licensed spectrum provides for exclusive use of a portion of a spectrum,generally by virtue of a mobile network operator purchasing a licensefrom a government regulatory body. In at least one embodiment, sharedspectrum may fall between licensed and unlicensed spectrum, whereintechnical rules or limitations may be required to access a spectrum, buta spectrum may still be shared by multiple operators and/or multipleRATs. In at least one embodiment, for example, a holder of a license fora portion of licensed spectrum may provide licensed shared access (LSA)to share that spectrum with other parties, e.g., with suitablelicensee-determined conditions to gain access. In at least oneembodiment, at least one component shown or described with respect toFIG. 44 is used to implement techniques and/or functions described inconnection with FIGS. 1-15B.

FIG. 45 provides an example illustration of a 5G mobile communicationssystem in which a plurality of different types of devices is used, inaccordance with at least one embodiment. In at least one embodiment, asshown in FIG. 45 , a first base station 4518 may be provided to a largecell or macro cell in which transmission of signals is over severalkilometers. In at least one embodiment, however, system may also supporttransmission via a very small cell such as transmitted by a secondinfrastructure equipment 4516 which transmits and receives signals overa distance of hundreds of meters thereby forming a so called “Pico”cell. In at least one embodiment, a third type of infrastructureequipment 4512 may transmit and receive signals over a distance of tensof meters and therefore can be used to form a so called “Femto” cell.

In at least one embodiment, also shown in FIG. 45 , different types ofcommunications devices may be used to transmit and receive signals viadifferent types of infrastructure equipment 4512, 4516, 4518 andcommunication of data may be adapted in accordance with different typesof infrastructure equipment using different communications parameters.In at least one embodiment, conventionally, a mobile communicationsdevice may be configured to communicate data to and from a mobilecommunications network via available communication resources of network.In at least one embodiment, a wireless access system is configured toprovide highest data rates to devices such as smart phones 4506. In atleast one embodiment, “internet of things” may be provided in which lowpower machine type communications devices transmit and receive data atvery low power, low bandwidth and may have a low complexity. In at leastone embodiment, an example of such a machine type communication device4514 may communicate via a Pico cell 4516. In at least one embodiment, avery high data rate and a low mobility may be characteristic ofcommunications with, for example, a television 4504 which may becommunicating via a Pico cell. In at least one embodiment, a very highdata rate and low latency may be required by a virtual reality headset4508. In at least one embodiment, a relay device 4510 may be deployed toextend size or coverage area of a given cell or network. In at least oneembodiment, at least one component shown or described with respect toFIG. 45 is used to implement techniques and/or functions described inconnection with FIGS. 1-15B.

FIG. 46 illustrates an example high level system 4600, in which at leastone embodiment may be used. In at least one embodiment, high levelsystem 4600 includes applications 4602, system software+libraries 4604,framework software 4606 and a datacenter infrastructure+resourceorchestrator 4608. In at least one embodiment, high level system 4600may be implemented as a cloud service, physical service, virtualservice, network service, and/or variations thereof.

In at least one embodiment, as shown in FIG. 46 , datacenterinfrastructure+resource orchestrator 4608 may include 5G radio resourceorchestrator 4610, GPU packet processing & I/O 4612, and node computingresources (“node C.R.s”) 4616(1)-4616(N), where “N” represents anywhole, positive integer. In at least one embodiment, node C.R.s4616(1)-4616(N) may include, but are not limited to, any number ofcentral processing units (“CPUs”) or other processors (includingaccelerators, field programmable gate arrays (FPGAs), graphicsprocessors (“GPUs”), etc.), memory devices (e.g., dynamic read-onlymemory), storage devices (e.g., solid state or disk drives), networkinput/output (“NW I/O”) devices, network switches, virtual machines(“VMs”), power modules, and cooling modules, etc. In at least oneembodiment, one or more node C.R.s from among node C.R.s 4616(1)-4616(N)may be a server having one or more of above-mentioned computingresources.

In at least one embodiment, 5G radio resource orchestrator 4610 mayconfigure or otherwise control one or more node C.R.s 4616(1)-4616(N)and/or other various components and resources a 5G network architecturemay comprise. In at least one embodiment, 5G radio resource orchestrator4610 may include a software design infrastructure (“SDI”) managemententity for high level system 4600. In at least one embodiment, 5G radioresource orchestrator 4610 may include hardware, software, or somecombination thereof. In at least one embodiment, 5G radio resourceorchestrator 4610 may be utilized to configure or otherwise controlvarious medium access control sublayers, radio access networks, physicallayers or sublayers, and/or variations thereof, which may be part of a5G network architecture. In at least one embodiment, 5G radio resourceorchestrator 4610 may configure or allocate grouped compute, network,memory or storage resources to support one or more workloads which maybe executed as part of a 5G network architecture.

In at least one embodiment, GPU packet processing & I/O 4612 mayconfigure or otherwise process various inputs and outputs, as well aspackets such as data packets, which may be transmitted/received as partof a 5G network architecture, which may be implemented by high levelsystem 4600. In at least one embodiment, a packet may be data formattedto be provided by a network and may be typically divided into controlinformation and payload (i.e., user data). In at least one embodiment,types of packets may include Internet Protocol version 4 (IPv4) packets,Internet Protocol version 6 (IPv6) packets, and Ethernet II framepackets. In at least one embodiment, control data of a data packet maybe classified into data integrity fields and semantic fields. In atleast one embodiment, network connections that a data packet may bereceived upon include a local area network, a wide-area network, avirtual private network, Internet, an intranet, an extranet, a publicswitched telephone network, an infrared network, a wireless network, asatellite network, and any combination thereof.

In at least one embodiment, framework software 4606 includes an AI ModelArchitecture+Training+Use Cases 4622. In at least one embodiment, AIModel Architecture+Training+Use Cases 4622 may include tools, services,software, or other resources to train one or more machine learningmodels or predict or infer information using one or more machinelearning models according to one or more embodiments. For example, in atleast one embodiment, a machine learning model may be trained bycalculating weight parameters according to a neural network architectureusing software and computing resources described above with respect tohigh level system 4600. In at least one embodiment, trained machinelearning models corresponding to one or more neural networks may be usedto infer or predict information using resources described above withrespect to high level system 4600 by using weight parameters calculatedthrough one or more training techniques. In at least one embodiment,framework software 4606 may include a framework to support systemsoftware+libraries 4604 and applications 4602.

In at least one embodiment, system software+libraries 4604 orapplications 4602 may respectively include web-based service software orapplications, such as those provided by Amazon Web Services, GoogleCloud and Microsoft Azure. In at least one embodiment, frameworksoftware 4606 may include, but is not limited to, a type of free andopen-source software web application framework such as Apache Spark™(hereinafter “Spark”). In at least one embodiment, systemsoftware+libraries 4604 may include software used by at least portionsof node C.R.s 4616(1)-4616(N). In at least one embodiment, one or moretypes of software may include, but are not limited to, Internet web pagesearch software, e-mail virus scan software, database software, andstreaming video content software.

In at least one embodiment, PHY 4618 is a set of system software andlibraries configured to provide an interface with a physical layer of awireless technology, which may be a physical layer such as a 5G NewRadio (NR) physical layer. In at least one embodiment, an NR physicallayer utilizes a flexible and scalable design and may comprise variouscomponents and technologies, such as modulation schemes, waveformstructures, frame structures, reference signals, multi-antennatransmission and channel coding.

In at least one embodiment, a NR physical layer supports quadraturephase shift keying (QPSK), 16 quadrature amplitude modulation (QAM), 64QAM and 256 QAM modulation formats. In at least one embodiment,different modulation schemes for different user entity (UE) categoriesmay also be included in a NR physical layer. In at least one embodiment,a NR physical layer may utilize cyclic prefix orthogonal frequencydivision multiplexing (CP-OFDM) with a scalable numerology (subcarrierspacing, cyclic prefix) in both uplink (UL) and downlink (DL) up to atleast 52.6 GHz. In at least one embodiment, a NR physical layer maysupport discrete Fourier transform spread orthogonal frequency divisionmultiplexing (DFT-SOFDM) in UL for coverage-limited scenarios, withsingle stream transmissions (that is, without spatial multiplexing).

In at least one embodiment, a NR frame supports time division duplex(TDD) and frequency division duplex (FDD) transmissions and operation inboth licensed and unlicensed spectrum, which enables very low latency,fast hybrid automatic repeat request (HARQ) acknowledgements, dynamicTDD, coexistence with LTE and transmissions of variable length (forexample, short duration for ultra-reliable low-latency communications(URLLC) and long duration for enhanced mobile broadband (eMBB)). In atleast one embodiment, NR frame structure follows three key designprinciples to enhance forward compatibility and reduce interactionsbetween different features.

In at least one embodiment, a first principle is that transmissions areself-contained, which can refer to a scheme in which data in a slot andin a beam are decodable on its own without dependency on other slots andbeams. In at least one embodiment, this implies that reference signalsrequired for demodulation of data are included in a given slot and agiven beam. In at least one embodiment, a second principle is thattransmissions are well confined in time and frequency, which results ina scheme in which new types of transmissions in parallel with legacytransmissions may be introduced. In at least one embodiment, a thirdprinciple is avoiding static and/or strict timing relations across slotsand across different transmission directions. In at least oneembodiment, usage of a third principle can entail utilizing asynchronoushybrid automatic repeat request (HARQ) instead of predefinedretransmission time.

In at least one embodiment, NR frame structure also allows for rapidHARQ acknowledgement, in which decoding is performed during reception ofDL data and HARQ acknowledgement is prepared by a UE during a guardperiod, when switching from DL reception to UL transmission. In at leastone embodiment, to obtain low latency, a slot (or a set of slots in caseof slot aggregation) is front-loaded with control signals and referencesignals at a beginning of a slot (or set of slots).

In at least one embodiment, NR has an ultra-lean design that minimizesalways-on transmissions to enhance network energy efficiency and ensureforward compatibility. In at least one embodiment, reference signals inNR are transmitted only when necessary. In at least one embodiment, fourmain reference signals are demodulation reference signal (DMRS),phase-tracking reference signal (PTRS), sounding reference signal (SRS)and channel-state information reference signal (CSI-RS).

In at least one embodiment, DMRS is used to estimate a radio channel fordemodulation. In at least one embodiment, DMRS is UE-specific, can bebeamformed, confined in a scheduled resource, and transmitted only whennecessary, both in DL and UL. In at least one embodiment, to supportmultiple-layer multiple-input, multiple-output (MIMO) transmission,multiple orthogonal DMRS ports can be scheduled, one for each layer. Inat least one embodiment, a basic DMRS pattern is front loaded, as a DMRSdesign takes into account an early decoding requirement to supportlow-latency applications. In at least one embodiment, for low-speedscenarios, DMRS uses low density in a time domain. In at least oneembodiment, however, for high-speed scenarios, a time density of DMRS isincreased to track fast changes in a radio channel.

In at least one embodiment, PTRS is introduced in NR to enablecompensation of oscillator phase noise. In at least one embodiment,typically, phase noise increases as a function of oscillator carrierfrequency. In at least one embodiment, PTRS can therefore be utilized athigh carrier frequencies (such as mmWave) to mitigate phase noise. In atleast one embodiment, PTRS is UE-specific, confined in a scheduledresource and can be beamformed. In at least one embodiment, PTRS isconfigurable depending on a quality of oscillators, carrier frequency,OFDM sub-carrier spacing, and modulation and coding schemes used fortransmission.

In at least one embodiment, SRS is transmitted in UL to perform channelstate information (CSI) measurements mainly for scheduling and linkadaptation. In at least one embodiment, for NR, SRS is also utilized forreciprocity-based precoder design for massive MIMO and UL beammanagement. In at least one embodiment, SRS has a modular and flexibledesign to support different procedures and UE capabilities. In at leastone embodiment, an approach for channel state information referencesignal (CSI-RS) is similar.

In at least one embodiment, NR employs different antenna solutions andtechniques depending on which part of a spectrum is used for itsoperation. In at least one embodiment, for lower frequencies, a low tomoderate number of active antennas (up to around 32 transmitter chains)is assumed and FDD operation is common. In at least one embodiment,acquisition of CSI requires transmission of CSI-RS in a DL and CSIreporting in an UL. In at least one embodiment, limited bandwidthsavailable in this frequency region require high spectral efficiencyenabled by multi-user MIMO (MU-MIMO) and higher order spatialmultiplexing, which is achieved via higher resolution CSI reportingcompared with LTE.

In at least one embodiment, for higher frequencies, a larger number ofantennas can be employed in a given aperture, which increases acapability for beamforming and multiuser (MU)-MIMO. In at least oneembodiment, here, spectrum allocations are of TDD type andreciprocity-based operation is assumed. In at least one embodiment,high-resolution CSI in a form of explicit channel estimations isacquired by UL channel sounding. In at least one embodiment, suchhigh-resolution CSI enables sophisticated precoding algorithms to beemployed at a base station (BS). In at least one embodiment, for evenhigher frequencies (in mmWave range) an analog beamformingimplementation is typically required currently, which limitstransmission to a single beam direction per time unit and radio chain.In at least one embodiment, since an isotropic antenna element is verysmall in this frequency region owing to a short carrier wavelength, agreat number of antenna elements is required to maintain coverage. In atleast one embodiment, beamforming needs to be applied at bothtransmitter and receiver ends to combat increased path loss, even forcontrol channel transmission.

In at least one embodiment, to support these diverse use cases, NRfeatures a highly flexible but unified CSI framework, in which there isreduced coupling between CSI measurement, CSI reporting and an actual DLtransmission in NR compared with LTE. In at least one embodiment, NRalso supports more advanced schemes such as multi-point transmission andcoordination. In at least one embodiment, control and data transmissionsfollow a self-contained principle, where all information required todecode a transmission (such as accompanying DMRS) is contained within atransmission itself. In at least one embodiment, as a result, a networkcan seamlessly change a transmission point or beam as a UE moves in anetwork.

In at least one embodiment, MAC 4620 is a set of system software andlibraries configured to provide an interface with a medium accesscontrol (MAC) layer, which may be part of a 5G network architecture. Inat least one embodiment, a MAC layer controls hardware responsible forinteraction with a wired, optical, or wireless transmission medium. Inat least one embodiment, MAC provides flow control and multiplexing fora transmission medium.

In at least one embodiment, a MAC sublayer provides an abstraction of aphysical layer such that complexities of a physical link control areinvisible to a logical link control (LLC) and upper layers of a networkstack. In at least one embodiment, any LLC sublayer (and higher layers)may be used with any MAC. In at least one embodiment, any MAC can beused with any physical layer, independent of transmission medium. In atleast one embodiment, a MAC sublayer, when sending data to anotherdevice on a network, encapsulates higher-level frames into framesappropriate for a transmission medium, adds a frame check sequence toidentify transmission errors, and then forwards data to a physical layeras soon as appropriate channel access method permits it. In at least oneembodiment, MAC is also responsible for compensating for collisions if ajam signal is detected, in which a MAC may initiate retransmission.

In at least one embodiment, applications 4602 may include one or moretypes of applications used by at least portions of node C.R.s4616(1)-4616(N) and/or framework software 4606. In at least oneembodiment, one or more types of applications may include, but are notlimited to, any number of a genomics application, a cognitive compute,and a machine learning application, including training or inferencingsoftware, machine learning framework software (e.g., PyTorch,TensorFlow, Caffe, etc.) or other machine learning applications used inconjunction with one or more embodiments.

In at least one embodiment, RAN APIs 4614 may be a set of subroutinedefinitions, communication protocols, and/or software tools that providea method of communication with components of a radio access network(RAN) which may be part of a 5G network architecture. In at least oneembodiment, a radio access network is part of a network communicationssystem and may implement a radio access technology. In at least oneembodiment, radio access network functionality is typically provided bya silicon chip residing in both a core network as well as userequipment. Further information regarding a radio access network can befound in the description of FIG. 44 .

In at least one embodiment, high level system 4600 may use CPUs,application-specific integrated circuits (ASICs), GPUs, FPGAs, or otherhardware to perform training, inferencing, and/or other variousprocesses using above-described resources. In at least one embodiment,moreover, one or more software and/or hardware resources described abovemay be configured as a service to allow users to train or performinginferencing of information, such as image recognition, speechrecognition, or other artificial intelligence services, as well as otherservices such as services that allow users to configure and implementvarious aspects of a 5G network architecture. In at least oneembodiment, at least one component shown or described with respect toFIG. 46 is used to implement techniques and/or functions described inconnection with FIGS. 1-15B.

FIG. 47 illustrates an architecture of a system 4700 of a network, inaccordance with at least one embodiment. In at least one embodiment,system 4700 is shown to include a user equipment (UE) 4702 and a UE4704. In at least one embodiment, UEs 4702 and 4704 are illustrated assmartphones (e.g., handheld touchscreen mobile computing devicesconnectable to one or more cellular networks) but may also comprise anymobile or non-mobile computing device, such as Personal Data Assistants(PDAs), pagers, laptop computers, desktop computers, wireless handsets,or any computing device including a wireless communications interface.

In at least one embodiment, any of UEs 4702 and 4704 can comprise anInternet of Things (IoT) UE, which can comprise a network access layerdesigned for low-power IoT applications utilizing short-lived UEconnections. In at least one embodiment, an IoT UE can utilizetechnologies such as machine-to-machine (M2M) or machine-typecommunications (MTC) for exchanging data with an MTC server or devicevia a public land mobile network (PLMN), Proximity-Based Service (ProSe)or device-to-device (D2D) communication, sensor networks, or IoTnetworks. In at least one embodiment, a M2M or MTC exchange of data maybe a machine-initiated exchange of data. In at least one embodiment, anIoT network describes interconnecting IoT UEs, which may includeuniquely identifiable embedded computing devices (within Internetinfrastructure), with short-lived connections. In at least oneembodiment, an IoT UEs may execute background applications (e.g., keepalive messages, status updates, etc.) to facilitate connections of anIoT network.

In at least one embodiment, UEs 4702 and 4704 may be configured toconnect, e.g., communicatively couple, with a radio access network (RAN)4716. In at least one embodiment, RAN 4716 may be, for example, anEvolved Universal Mobile Telecommunications System (UMTS) TerrestrialRadio Access Network (E-UTRAN), a NextGen RAN (NG RAN), or some othertype of RAN. In at least one embodiment, UEs 4702 and 4704 utilizeconnections 4712 and 4714, respectively, each of which comprises aphysical communications interface or layer. In at least one embodiment,connections 4712 and 4714 are illustrated as an air interface to enablecommunicative coupling, and can be consistent with cellularcommunications protocols, such as a Global System for MobileCommunications (GSM) protocol, a code-division multiple access (CDMA)network protocol, a Push-to-Talk (PTT) protocol, a PTT over Cellular(POC) protocol, a Universal Mobile Telecommunications System (UMTS)protocol, a 3GPP Long Term Evolution (LTE) protocol, a fifth generation(5G) protocol, a New Radio (NR) protocol, and variations thereof.

In at least one embodiment, UEs 4702 and 4704 may further directlyexchange communication data via a ProSe interface 4706. In at least oneembodiment, ProSe interface 4706 may alternatively be referred to as asidelink interface comprising one or more logical channels, includingbut not limited to a Physical Sidelink Control Channel (PSCCH), aPhysical Sidelink Shared Channel (PSSCH), a Physical Sidelink DiscoveryChannel (PSDCH), and a Physical Sidelink Broadcast Channel (PSBCH).

In at least one embodiment, UE 4704 is shown to be configured to accessan access point (AP) 4710 via connection 4708. In at least oneembodiment, connection 4708 can comprise a local wireless connection,such as a connection consistent with any IEEE 802.11 protocol, whereinAP 4710 would comprise a wireless fidelity (WiFi®) router. In at leastone embodiment, AP 4710 is shown to be connected to an Internet withoutconnecting to a core network of a wireless system.

In at least one embodiment, RAN 4716 can include one or more accessnodes that enable connections 4712 and 4714. In at least one embodiment,these access nodes (ANs) can be referred to as base stations (BSs),NodeBs, evolved NodeBs (eNBs), next Generation NodeBs (gNB), RAN nodes,and so forth, and can comprise ground stations (e.g., terrestrial accesspoints) or satellite stations providing coverage within a geographicarea (e.g., a cell). In at least one embodiment, RAN 4716 may includeone or more RAN nodes for providing macrocells, e.g., macro RAN node4718, and one or more RAN nodes for providing femtocells or picocells(e.g., cells having smaller coverage areas, smaller user capacity, orhigher bandwidth compared to macrocells), e.g., low power (LP) RAN node4720.

In at least one embodiment, any of RAN nodes 4718 and 4720 can terminatean air interface protocol and can be a first point of contact for UEs4702 and 4704. In at least one embodiment, any of RAN nodes 4718 and4720 can fulfill various logical functions for RAN 4716 including, butnot limited to, radio network controller (RNC) functions such as radiobearer management, uplink and downlink dynamic radio resource managementand data packet scheduling, and mobility management.

In at least one embodiment, UEs 4702 and 4704 can be configured tocommunicate using Orthogonal Frequency-Division Multiplexing (OFDM)communication signals with each other or with any of RAN nodes 4718 and4720 over a multi-carrier communication channel in accordance variouscommunication techniques, such as, but not limited to, an OrthogonalFrequency Division Multiple Access (OFDMA) communication technique(e.g., for downlink communications) or a Single Carrier FrequencyDivision Multiple Access (SC-FDMA) communication technique (e.g., foruplink and ProSe or sidelink communications), and/or variations thereof.In at least one embodiment, OFDM signals can comprise a plurality oforthogonal sub-carriers.

In at least one embodiment, a downlink resource grid can be used fordownlink transmissions from any of RAN nodes 4718 and 4720 to UEs 4702and 4704, while uplink transmissions can utilize similar techniques. Inat least one embodiment, a grid can be a time frequency grid, called aresource grid or time-frequency resource grid, which is a physicalresource in a downlink in each slot. In at least one embodiment, such atime frequency plane representation is a common practice for OFDMsystems, which makes it intuitive for radio resource allocation. In atleast one embodiment, each column and each row of a resource gridcorresponds to one OFDM symbol and one OFDM subcarrier, respectively. Inat least one embodiment, a duration of a resource grid in a time domaincorresponds to one slot in a radio frame. In at least one embodiment, asmallest time-frequency unit in a resource grid is denoted as a resourceelement. In at least one embodiment, each resource grid comprises anumber of resource blocks, which describe a mapping of certain physicalchannels to resource elements. In at least one embodiment, each resourceblock comprises a collection of resource elements. In at least oneembodiment, in a frequency domain, this may represent a smallestquantity of resources that currently can be allocated. In at least oneembodiment, there are several different physical downlink channels thatare conveyed using such resource blocks.

In at least one embodiment, a physical downlink shared channel (PDSCH)may carry user data and higher-layer signaling to UEs 4702 and 4704. Inat least one embodiment, a physical downlink control channel (PDCCH) maycarry information about a transport format and resource allocationsrelated to PDSCH channel, among other things. In at least oneembodiment, it may also inform UEs 4702 and 4704 about a transportformat, resource allocation, and HARQ (Hybrid Automatic Repeat Request)information related to an uplink shared channel. In at least oneembodiment, typically, downlink scheduling (assigning control and sharedchannel resource blocks to UE 4702 within a cell) may be performed atany of RAN nodes 4718 and 4720 based on channel quality information fedback from any of UEs 4702 and 4704. In at least one embodiment, downlinkresource assignment information may be sent on a PDCCH used for (e.g.,assigned to) each of UEs 4702 and 4704.

In at least one embodiment, a PDCCH may use control channel elements(CCEs) to convey control information. In at least one embodiment, beforebeing mapped to resource elements, PDCCH complex valued symbols mayfirst be organized into quadruplets, which may then be permuted using asub-block interleaver for rate matching. In at least one embodiment,each PDCCH may be transmitted using one or more of these CCEs, whereeach CCE may correspond to nine sets of four physical resource elementsknown as resource element groups (REGs). In at least one embodiment,four Quadrature Phase Shift Keying (QPSK) symbols may be mapped to eachREG. In at least one embodiment, PDCCH can be transmitted using one ormore CCEs, depending on a size of a downlink control information (DCI)and a channel condition. In at least one embodiment, there can be fouror more different PDCCH formats defined in LTE with different numbers ofCCEs (e.g., aggregation level, L=1, 2, 4, or 8).

In at least one embodiment, an enhanced physical downlink controlchannel (EPDCCH) that uses PDSCH resources may be utilized for controlinformation transmission. In at least one embodiment, EPDCCH may betransmitted using one or more enhanced control channel elements (ECCEs).In at least one embodiment, each ECCE may correspond to nine sets offour physical resource elements known as an enhanced resource elementgroup (EREG). In at least one embodiment, an ECCE may have other numbersof EREGs in some situations.

In at least one embodiment, RAN 4716 is shown to be communicativelycoupled to a core network (CN) 4738 via an S1 interface 4722. In atleast one embodiment, CN 4738 may be an evolved packet core (EPC)network, a NextGen Packet Core (NPC) network, or some other type of CN.In at least one embodiment, S1 interface 4722 is split into two parts:S1-U interface 4726, which carries traffic data between RAN nodes 4718and 4720 and serving gateway (S-GW) 4730, and a S1-mobility managemententity (MME) interface 4724, which is a signaling interface between RANnodes 4718 and 4720 and MMEs 4728.

In at least one embodiment, CN 4738 comprises MMEs 4728, S-GW 4730,Packet Data Network (PDN) Gateway (P-GW) 4734, and a home subscriberserver (HSS) 4732. In at least one embodiment, MMEs 4728 may be similarin function to a control plane of legacy Serving General Packet RadioService (GPRS) Support Nodes (SGSN). In at least one embodiment, MMEs4728 may manage mobility aspects in access such as gateway selection andtracking area list management. In at least one embodiment, HSS 4732 maycomprise a database for network users, including subscription relatedinformation to support a network entities' handling of communicationsessions. In at least one embodiment, CN 4738 may comprise one orseveral HSSs 4732, depending on a number of mobile subscribers, on acapacity of an equipment, on an organization of a network, etc. In atleast one embodiment, HSS 4732 can provide support for routing/roaming,authentication, authorization, naming/addressing resolution, locationdependencies, etc.

In at least one embodiment, S-GW 4730 may terminate a S1 interface 4722towards RAN 4716, and routes data packets between RAN 4716 and CN 4738.In at least one embodiment, S-GW 4730 may be a local mobility anchorpoint for inter-RAN node handovers and also may provide an anchor forinter-3GPP mobility. In at least one embodiment, other responsibilitiesmay include lawful intercept, charging, and some policy enforcement.

In at least one embodiment, P-GW 4734 may terminate an SGi interfacetoward a PDN. In at least one embodiment, P-GW 4734 may route datapackets between an EPC network 4738 and external networks such as anetwork including application server 4740 (alternatively referred to asapplication function (AF)) via an Internet Protocol (IP) interface 4742.In at least one embodiment, application server 4740 may be an elementoffering applications that use IP bearer resources with a core network(e.g., UMTS Packet Services (PS) domain, LTE PS data services, etc.). Inat least one embodiment, P-GW 4734 is shown to be communicativelycoupled to an application server 4740 via an IP communications interface4742. In at least one embodiment, application server 4740 can also beconfigured to support one or more communication services (e.g.,Voice-over-Internet Protocol (VoIP) sessions, PTT sessions, groupcommunication sessions, social networking services, etc.) for UEs 4702and 4704 via CN 4738.

In at least one embodiment, P-GW 4734 may further be a node for policyenforcement and charging data collection. In at least one embodiment,policy and Charging Enforcement Function (PCRF) 4736 is a policy andcharging control element of CN 4738. In at least one embodiment, in anon-roaming scenario, there may be a single PCRF in a Home Public LandMobile Network (HPLMN) associated with a UE's Internet ProtocolConnectivity Access Network (IP-CAN) session. In at least oneembodiment, in a roaming scenario with local breakout of traffic, theremay be two PCRFs associated with a UE's IP-CAN session: a Home PCRF(H-PCRF) within a HPLMN and a Visited PCRF (V-PCRF) within a VisitedPublic Land Mobile Network (VPLMN). In at least one embodiment, PCRF4736 may be communicatively coupled to application server 4740 via P-GW4734. In at least one embodiment, application server 4740 may signalPCRF 4736 to indicate a new service flow and select an appropriateQuality of Service (QoS) and charging parameters. In at least oneembodiment, PCRF 4736 may provision this rule into a Policy and ChargingEnforcement Function (PCEF) (not shown) with an appropriate traffic flowtemplate (TFT) and QoS class of identifier (QCI), which commences a QoSand charging as specified by application server 4740. In at least oneembodiment, at least one component shown or described with respect toFIG. 47 is used to implement techniques and/or functions described inconnection with FIGS. 1-15B.

FIG. 48 illustrates example components of a device 4800 in accordancewith at least one embodiment. In at least one embodiment, device 4800may include application circuitry 4804, baseband circuitry 4808, RadioFrequency (RF) circuitry 4810, front-end module (FEM) circuitry 4802,one or more antennas 4812, and power management circuitry (PMC) 4806coupled together at least as shown. In at least one embodiment,components of illustrated device 4800 may be included in a UE or a RANnode. In at least one embodiment, device 4800 may include less elements(e.g., a RAN node may not utilize application circuitry 4804, andinstead include a processor/controller to process IP data received froman EPC). In at least one embodiment, device 4800 may include additionalelements such as, for example, memory/storage, display, camera, sensor,or input/output (I/O) interface. In at least one embodiment, componentsdescribed below may be included in more than one device (e.g., saidcircuitries may be separately included in more than one device forCloud-RAN (C-RAN) implementations).

In at least one embodiment, application circuitry 4804 may include oneor more application processors. In at least one embodiment, applicationcircuitry 4804 may include circuitry such as, but not limited to, one ormore single-core or multi-core processors. In at least one embodiment,processor(s) may include any combination of general purpose processorsand dedicated processors (e.g., graphics processors, applicationprocessors, etc.). In at least one embodiment, processors may be coupledwith or may include memory/storage and may be configured to executeinstructions stored in memory/storage to enable various applications oroperating systems to run on device 4800. In at least one embodiment,processors of application circuitry 4804 may process IP data packetsreceived from an EPC.

In at least one embodiment, baseband circuitry 4808 may includecircuitry such as, but not limited to, one or more single-core ormulti-core processors. In at least one embodiment, baseband circuitry4808 may include one or more baseband processors or control logic toprocess baseband signals received from a receive signal path of RFcircuitry 4810 and to generate baseband signals for a transmit signalpath of RF circuitry 4810. In at least one embodiment, basebandprocessing circuitry 4808 may interface with application circuitry 4804for generation and processing of baseband signals and for controllingoperations of RF circuitry 4810. In at least one embodiment, basebandcircuitry 4808 may include a third generation (3G) baseband processor4808A, a fourth generation (4G) baseband processor 4808B, a fifthgeneration (5G) baseband processor 4808C, or other baseband processor(s)4808D for other existing generations, generations in development or tobe developed (e.g., second generation (2G), sixth generation (6G),etc.). In at least one embodiment, baseband circuitry 4808 (e.g., one ormore of base-band processors 4808A-D) may handle various radio controlfunctions that enable communication with one or more radio networks viaRF circuitry 4810. In at least one embodiment, some, or all of afunctionality of baseband processors 4808A-D may be included in modulesstored in memory 4808G and executed via a Central Processing Unit (CPU)4808E. In at least one embodiment, radio control functions may include,but are not limited to, signal modulation/demodulation,encoding/decoding, radio frequency shifting, etc. In at least oneembodiment, modulation/demodulation circuitry of baseband circuitry 4808may include Fast-Fourier Transform (FFT), precoding, or constellationmapping/demapping functionality. In at least one embodiment,encoding/decoding circuitry of baseband circuitry 4808 may includeconvolution, tail biting convolution, turbo, Viterbi, or Low DensityParity Check (LDPC) encoder/decoder functionality.

In at least one embodiment, baseband circuitry 4808 may include one ormore audio digital signal processor(s) (DSP) 4808F. In at least oneembodiment, audio DSP(s) 4808F may be include elements forcompression/decompression and echo cancellation and may include othersuitable processing elements in other embodiments. In at least oneembodiment, components of baseband circuitry may be suitably combined ina single chip, a single chipset, or disposed on a same circuit board insome embodiments. In at least one embodiment, some, or all ofconstituent components of baseband circuitry 4808 and applicationcircuitry 4804 may be implemented together such as, for example, on asystem on a chip (SOC).

In at least one embodiment, baseband circuitry 4808 may provide forcommunication compatible with one or more radio technologies. In atleast one embodiment, baseband circuitry 4808 may support communicationwith an evolved universal terrestrial radio access network (EUTRAN) orother wireless metropolitan area networks (WMAN), a wireless local areanetwork (WLAN), a wireless personal area network (WPAN). In at least oneembodiment, baseband circuitry 4808 is configured to support radiocommunications of more than one wireless protocol and may be referred toas multimode baseband circuitry.

In at least one embodiment, RF circuitry 4810 may enable communicationwith wireless networks using modulated electromagnetic radiation througha non-solid medium. In at least one embodiment, RF circuitry 4810 mayinclude switches, filters, amplifiers, etc. to facilitate communicationwith a wireless network. In at least one embodiment, RF circuitry 4810may include a receive signal path which may include circuitry todown-convert RF signals received from FEM circuitry 4802 and providebaseband signals to baseband circuitry 4808. In at least one embodiment,RF circuitry 4810 may also include a transmit signal path which mayinclude circuitry to up-convert baseband signals provided by basebandcircuitry 4808 and provide RF output signals to FEM circuitry 4802 fortransmission.

In at least one embodiment, receive signal path of RF circuitry 4810 mayinclude mixer circuitry 4810 a, amplifier circuitry 4810 b and filtercircuitry 4810 c. In at least one embodiment, a transmit signal path ofRF circuitry 4810 may include filter circuitry 4810 c and mixercircuitry 4810 a. In at least one embodiment, RF circuitry 4810 may alsoinclude synthesizer circuitry 4810 d for synthesizing a frequency foruse by mixer circuitry 4810 a of a receive signal path and a transmitsignal path. In at least one embodiment, mixer circuitry 4810 a of areceive signal path may be configured to down-convert RF signalsreceived from FEM circuitry 4802 based on a synthesized frequencyprovided by synthesizer circuitry 4810 d. In at least one embodiment,amplifier circuitry 4810 b may be configured to amplify down-convertedsignals and filter circuitry 4810 c may be a low-pass filter (LPF) orband-pass filter (BPF) configured to remove unwanted signals fromdown-converted signals to generate output baseband signals. In at leastone embodiment, output baseband signals may be provided to basebandcircuitry 4808 for further processing. In at least one embodiment,output baseband signals may be zero-frequency baseband signals, althoughthis is not a requirement. In at least one embodiment, mixer circuitry4810 a of a receive signal path may comprise passive mixers.

In at least one embodiment, mixer circuitry 4810 a of a transmit signalpath may be configured to up-convert input baseband signals based on asynthesized frequency provided by synthesizer circuitry 4810 d togenerate RF output signals for FEM circuitry 4802. In at least oneembodiment, baseband signals may be provided by baseband circuitry 4808and may be filtered by filter circuitry 4810 c.

In at least one embodiment, mixer circuitry 4810 a of a receive signalpath and mixer circuitry 4810 a of a transmit signal path may includetwo or more mixers and may be arranged for quadrature down conversionand up conversion, respectively. In at least one embodiment, mixercircuitry 4810 a of a receive signal path and mixer circuitry 4810 a ofa transmit signal path may include two or more mixers and may bearranged for image rejection (e.g., Hartley image rejection). In atleast one embodiment, mixer circuitry 4810 a of a receive signal pathand mixer circuitry 4810 a may be arranged for direct down conversionand direct up conversion, respectively. In at least one embodiment,mixer circuitry 4810 a of a receive signal path and mixer circuitry 4810a of a transmit signal path may be configured for super-heterodyneoperation.

In at least one embodiment, output baseband signals and input basebandsignals may be analog baseband signals. In at least one embodiment,output baseband signals and input baseband signals may be digitalbaseband signals. In at least one embodiment, RF circuitry 4810 mayinclude analog-to-digital converter (ADC) and digital-to-analogconverter (DAC) circuitry and baseband circuitry 4808 may include adigital baseband interface to communicate with RF circuitry 4810.

In at least one embodiment, a separate radio IC circuitry may beprovided for processing signals for each spectrum In at least oneembodiment, synthesizer circuitry 4810 d may be a fractional-Nsynthesizer or a fractional N/N+1 synthesizer. In at least oneembodiment, synthesizer circuitry 4810 d may be a delta-sigmasynthesizer, a frequency multiplier, or a synthesizer comprising aphase-locked loop with a frequency divider.

In at least one embodiment, synthesizer circuitry 4810 d may beconfigured to synthesize an output frequency for use by mixer circuitry4810 a of RF circuitry 4810 based on a frequency input and a dividercontrol input. In at least one embodiment, synthesizer circuitry 4810 dmay be a fractional N/N+1 synthesizer.

In at least one embodiment, frequency input may be provided by avoltage-controlled oscillator (VCO). In at least one embodiment, dividercontrol input may be provided by either baseband circuitry 4808 orapplications processor 4804 depending on a desired output frequency. Inat least one embodiment, a divider control input (e.g., N) may bedetermined from a look-up table based on a channel indicated byapplications processor 4804.

In at least one embodiment, synthesizer circuitry 4810 d of RF circuitry4810 may include a divider, a delay-locked loop (DLL), a multiplexer anda phase accumulator. In at least one embodiment, divider may be a dualmodulus divider (DMD) and phase accumulator may be a digital phaseaccumulator (DPA). In at least one embodiment, DMD may be configured todivide an input signal by either N or N+1 (e.g., based on a carry out)to provide a fractional division ratio. In at least one embodiment, DLLmay include a set of cascaded, tunable, delay elements, a phasedetector, a charge pump, and a D-type flip-flop. In at least oneembodiment, delay elements may be configured to break a VCO period upinto Nd equal packets of phase, where Nd is a number of delay elementsin a delay line. In at least one embodiment, in this way, DLL providesnegative feedback to help ensure that total delay through a delay lineis one VCO cycle.

In at least one embodiment, synthesizer circuitry 4810 d may beconfigured to generate a carrier frequency as an output frequency, whilein other embodiments, output frequency may be a multiple of a carrierfrequency (e.g., twice a carrier frequency, four times a carrierfrequency) and used in conjunction with quadrature generator and dividercircuitry to generate multiple signals at a carrier frequency withmultiple different phases with respect to each other. In at least oneembodiment, output frequency may be a LO frequency (fLO). In at leastone embodiment, RF circuitry 4810 may include an IQ/polar converter.

In at least one embodiment, FEM circuitry 4802 may include a receivesignal path which may include circuitry configured to operate on RFsignals received from one or more antennas 4812, amplify receivedsignals and provide amplified versions of received signals to RFcircuitry 4810 for further processing. In at least one embodiment, FEMcircuitry 4802 may also include a transmit signal path which may includecircuitry configured to amplify signals for transmission provided by RFcircuitry 4810 for transmission by one or more of one or more antennas4812. In at least one embodiment, amplification through a transmit orreceive signal paths may be done solely in RF circuitry 4810, solely inFEM 4802, or in both RF circuitry 4810 and FEM 4802.

In at least one embodiment, FEM circuitry 4802 may include a TX/RXswitch to switch between transmit mode and receive mode operation. In atleast one embodiment, FEM circuitry may include a receive signal pathand a transmit signal path. In at least one embodiment, a receive signalpath of FEM circuitry may include an LNA to amplify received RF signalsand provide amplified received RF signals as an output (e.g., to RFcircuitry 4810). In at least one embodiment, a transmit signal path ofFEM circuitry 4802 may include a power amplifier (PA) to amplify inputRF signals (e.g., provided by RF circuitry 4810), and one or morefilters to generate RF signals for subsequent transmission (e.g., by oneor more of one or more antennas 4812).

In at least one embodiment, PMC 4806 may manage power provided tobaseband circuitry 4808. In at least one embodiment, PMC 4806 maycontrol power-source selection, voltage scaling, battery charging, orDC-to-DC conversion. In at least one embodiment, PMC 4806 may often beincluded when device 4800 is capable of being powered by a battery, forexample, when device is included in a UE. In at least one embodiment,PMC 4806 may increase power conversion efficiency while providingdesirable implementation size and heat dissipation characteristics.

In at least one embodiment, PMC 4806 may be additionally oralternatively coupled with, and perform similar power managementoperations for, other components such as, but not limited to,application circuitry 4804, RF circuitry 4810, or FEM 4802.

In at least one embodiment, PMC 4806 may control, or otherwise be partof, various power saving mechanisms of device 4800. In at least oneembodiment, if device 4800 is in an RRC Connected state, where it isstill connected to a RAN node as it expects to receive traffic shortly,then it may enter a state known as Discontinuous Reception Mode (DRX)after a period of inactivity. In at least one embodiment, during thisstate, device 4800 may power down for brief intervals of time and thussave power.

In at least one embodiment, if there is no data traffic activity for anextended period of time, then device 4800 may transition off to an RRCIdle state, where it disconnects from a network and does not performoperations such as channel quality feedback, handover, etc. In at leastone embodiment, device 4800 goes into a very low power state and itperforms paging where again it periodically wakes up to listen to anetwork and then powers down again. In at least one embodiment, device4800 may not receive data in this state, in order to receive data, itmust transition back to RRC Connected state.

In at least one embodiment, an additional power saving mode may allow adevice to be unavailable to a network for periods longer than a paginginterval (ranging from seconds to a few hours). In at least oneembodiment, during this time, a device is totally unreachable to anetwork and may power down completely. In at least one embodiment, anydata sent during this time incurs a large delay and it is assumed delayis acceptable.

In at least one embodiment, processors of application circuitry 4804 andprocessors of baseband circuitry 4808 may be used to execute elements ofone or more instances of a protocol stack. In at least one embodiment,processors of baseband circuitry 4808, alone or in combination, may beused execute Layer 3, Layer 2, or Layer 1 functionality, whileprocessors of application circuitry 4808 may utilize data (e.g., packetdata) received from these layers and further execute Layer 4functionality (e.g., transmission communication protocol (TCP) and userdatagram protocol (UDP) layers). In at least one embodiment, layer 3 maycomprise a radio resource control (RRC) layer. In at least oneembodiment, Layer 2 may comprise a medium access control (MAC) layer, aradio link control (RLC) layer, and a packet data convergence protocol(PDCP) layer. In at least one embodiment, Layer 1 may comprise aphysical (PHY) layer of a UE/RAN node. In at least one embodiment, atleast one component shown or described with respect to FIG. 48 is usedto implement techniques and/or functions described in connection withFIGS. 1-15B.

FIG. 49 illustrates example interfaces of baseband circuitry, inaccordance with at least one embodiment. In at least one embodiment, asdiscussed above, baseband circuitry 4808 of FIG. 48 may compriseprocessors 4808A-4808E and a memory 4808G utilized by said processors.In at least one embodiment, each of processors 4808A-4808E may include amemory interface, 4902A-4902E, respectively, to send/receive datato/from memory 4808G.

In at least one embodiment, baseband circuitry 4808 may further includeone or more interfaces to communicatively couple to othercircuitries/devices, such as a memory interface 4904 (e.g., an interfaceto send/receive data to/from memory external to baseband circuitry4808), an application circuitry interface 4906 (e.g., an interface tosend/receive data to/from application circuitry 4804 of FIG. 48 ), an RFcircuitry interface 4908 (e.g., an interface to send/receive datato/from RF circuitry 4810 of FIG. 48 ), a wireless hardware connectivityinterface 4910 (e.g., an interface to send/receive data to/from NearField Communication (NFC) components, Bluetooth® components (e.g.,Bluetooth® Low Energy), Wi-Fi® components, and other communicationcomponents), and a power management interface 4912 (e.g., an interfaceto send/receive power or control signals to/from PMC 4806. In at leastone embodiment, at least one component shown or described with respectto FIG. 49 is used to implement techniques and/or functions described inconnection with FIGS. 1-15B.

FIG. 50 illustrates an example of an uplink channel, in accordance withat least one embodiment. In at least one embodiment, FIG. 50 illustratestransmitting and receiving data within a physical uplink shared channel(PUSCH) in 5G NR, which may be part of a physical layer of a mobiledevice network.

In at least one embodiment, Physical Uplink Shared Channel (PUSCH) in 5GNR is designated to carry multiplexed control information and userapplication data. In at least one embodiment, 5G NR provides much moreflexibility and reliability comparing to its predecessor, which in someexamples may be referred to as 4G LTE, including more elastic pilotarrangements and support for both cyclic prefix (CP)-OFDM and DiscreteFourier Transform spread (DFT-s)-OFDM waveforms. In at least oneembodiment, standard introduced filtered OFDM (f-OFDM) technique isutilized to add additional filtering to reduce Out-of-Band emission andimprove performance at higher modulation orders. In at least oneembodiment, modifications in Forward Error Correction (FEC) were imposedto replace Turbo Codes used in 4G LTE by Quasi-Cyclic Low Density ParityCheck (QC-LDPC) codes, which were proven to achieve better transmissionrates and provide opportunities for more efficient hardwareimplementations.

In at least one embodiment, transmission of 5G NR downlink and uplinkdata is organized into frames of 10 ms duration, each divided into 10subframes of 1 ms each. In at least one embodiment, subframes arecomposed of a variable number of slots, depending on a selectedsubcarrier spacing which is parameterized in 5G NR. In at least oneembodiment, a slot is built from 14 OFDMA symbols, each prepended with acyclic prefix. In at least one embodiment, a subcarrier that is locatedwithin a passband and is designated for transmission is called aResource Element (RE). In at least one embodiment, a group of 12neighboring RE in a same symbol form a Physical Resource Block (PRB).

In at least one embodiment, 5G NR standard defined two types ofreference signals associated with transmission within a PUSCH channel.In at least one embodiment, Demodulation Reference Signal (DMRS) is auser specific reference signal with high frequency density. In at leastone embodiment, DMRS is transmitted within dedicated orthogonalfrequency-division multiple access (OFDMA) symbols only and designatedfor frequency-selective channel estimation. In at least one embodiment,a number of DMRS symbols within a slot may vary between 1 and 4depending on configuration, where a denser DMRS symbol spacing in timeis designated for fast time-varying channels to obtain more accurateestimates within a coherence time of a channel. In at least oneembodiment, in a frequency domain, DMRS PRB are mapped within a wholetransmission allocation. In at least one embodiment, spacing between aDMRS resource element (RE) assigned for a same Antenna Port (AP) may bechosen between 2 and 3. In at least one embodiment, in a case of 2-2multiple-input, multiple-output (MIMO), a standard allows for orthogonalassignment of RE between AP. In at least one embodiment, a receiver mayperform partial single input, multiple output (SIMO) channel estimationbased on a DMRS RE prior to MIMO equalization, neglecting spatialcorrelation.

In at least one embodiment, a second type of reference signal is a PhaseTracking Reference Signal (PTRS). In at least one embodiment, PTRSsubcarriers are arranged in a comb structure having high density in atime domain. In at least one embodiment, it is used mainly in mmWavefrequency bands to track and correct phase noise, which is aconsiderable source of performance losses. In at least one embodiment,usage of PTRS is optional, as it may lower a total spectral efficiencyof a transmission when effects of phase noise are negligible.

In at least one embodiment, for transmission of data, a transport blockmay be generated from a MAC layer and given to a physical layer. In atleast one embodiment, a transport block may be data that is intended tobe transmitted. In at least one embodiment, a transmission in a physicallayer starts with grouped resource data, which may be referred to astransport blocks. In at least one embodiment, a transport block isreceived by a cyclic redundancy check (CRC) 5002. In at least oneembodiment, a cyclic redundancy check is appended to each transportblock for error detection. In at least one embodiment, a cyclicredundancy check is used for error detection in transport blocks. In atleast one embodiment, an entire transport block is used to calculate CRCparity bits and these parity bits are then attached to an end of atransport block. In at least one embodiment, minimum and maximum codeblock sizes are specified so blocks sizes are compatible with furtherprocesses. In at least one embodiment, an input block is segmented whenan input block is greater than a maximum code block size.

In at least one embodiment, a transport block is received and encoded bya low-density parity-check (LDPC) encode 5004. In at least oneembodiment, NR employs low-density parity-check (LDPC) codes for a datachannel and polar codes for a control channel. In at least oneembodiment, LDPC codes are defined by their parity-check matrices, witheach column representing a coded bit, and each row representing aparity-check equation. In at least one embodiment, LDPC codes aredecoded by exchanging messages between variables and parity checks in aniterative manner. In at least one embodiment, LDPC codes proposed for NRuse a quasi-cyclic structure, where a parity-check matrix is defined bya smaller base matrix. In at least one embodiment, each entry of thebase matrix represents either a Z×Z zero matrix or a shifted Z×Zidentity matrix

In at least one embodiment, an encoded transport block is received byrate match 5006. In at least one embodiment, an encoded block is used tocreate an output bit stream with a desired code rate. In at least oneembodiment, rate match 5006 is utilized to create an output bit streamto be transmitted with a desired code rate. In at least one embodiment,bits are selected and pruned from a buffer to create an output bitstream with a desired code rate. In at least one embodiment, a HybridAutomatic Repeat Request (HARQ) error correction scheme is incorporated.

In at least one embodiment, output bits are scrambled, which may aid inprivacy, in scramble 5008. In at least one embodiment, codewords arebit-wise multiplied with an orthogonal sequence and a UE-specificscrambling sequence. In at least one embodiment, output of scramble 5008may be input into modulation/mapping/precoding and other processes 5010.In at least one embodiment, various modulation, mapping, and precodingprocesses are performed.

In at least one embodiment, bits output from scramble 5008 are modulatedwith a modulation scheme, resulting in blocks of modulation symbols. Inat least one embodiment, scrambled codewords undergo modulation usingone of modulation schemes QPSK, 16 QAM, 64 QAM, resulting in a block ofmodulation symbols. In at least one embodiment, a channel interleaverprocess may be utilized that implements a first time mapping ofmodulation symbols onto a transmit waveform while ensuring that HARQinformation is present on both slots. In at least one embodiment,modulation symbols are mapped to various layers based on transmitantennas. In at least one embodiment, symbols may be precoded, in whichthey are divided into sets, and an Inverse Fast Fourier Transform may beperformed. In at least one embodiment, transport data and controlmultiplexing may be performed such that HARQ acknowledge (ACK)information is present in both slots and is mapped to resources arounddemodulation reference signals. In at least one embodiment, variousprecoding processes are performed.

In at least one embodiment, symbols are mapped to allocated physicalresource elements in resource element mapping 5012. In at least oneembodiment, allocation sizes may be limited to values whose primefactors are 2, 3 and 5. In at least one embodiment, symbols are mappedin increasing order beginning with subcarriers. In at least oneembodiment, subcarrier mapped modulation symbols data are orthogonalfrequency-division multiple access (OFDMA) modulated through IFFToperation in OFDMA modulation 5014. In at least one embodiment, timedomain representations of each symbol are concatenated and filteredusing transmit FIR filter to attenuate unwanted Out of Band emission toadjacent frequency bands caused by phase discontinuities and utilizationof different numerologies. In at least one embodiment, an output ofOFDMA modulation 5014 may be transmitted to be received and processed byanother system.

In at least one embodiment, a transmission may be received by OFDMAdemodulation 5016. In at least one embodiment, a transmission mayoriginate from user mobile devices over a cellular network, althoughother contexts may be present. In at least one embodiment, atransmission may be demodulated through IFFT processing. In at least oneembodiment, once OFDMA demodulation through IFFT processing has beenaccomplished, an estimation and correction of residual Sample TimeOffset (STO) and Carrier Frequency Offset (CFO) may be performed. In atleast one embodiment, both CFO and STO corrections have to be performedin frequency domain, because a received signal can be a superposition oftransmissions coming from multiple UEs multiplexed in frequency, eachsuffering from a specific residual synchronization error. In at leastone embodiment, residual CFO is estimated as a phase rotation betweenpilot subcarriers belonging to different OFDM symbols and corrected by acircular convolution operation in frequency domain.

In at least one embodiment, output of OFDMA demodulation 5016 may bereceived by resource element demapping 5018. In at least one embodiment,resource element demapping 5018 may determine symbols and demap symbolsfrom allocated physical resource elements. In at least one embodiment, achannel estimation and equalization is performed in channel estimation5020 in order to compensate for effects of multipath propagation. In atleast one embodiment, channel estimation 5020 may be utilized tominimize effects of noise originating from various transmission layersand antennae. In at least one embodiment, channel estimation 5020 maygenerate equalized symbols from an output of resource element demapping5018. In at least one embodiment, demodulation/demapping 5022 mayreceive equalized symbols from channel estimation 5020. In at least oneembodiment, equalized symbols are demapped and permuted through a layerdemapping operation. In at least one embodiment, a Maximum A PosterioriProbability (MAP) demodulation approach may be utilized to producevalues representing beliefs regarding a received bit being 0 or 1,expressed in a form of Log-Likelihood Ratio (LLR).

In at least one embodiment, soft-demodulated bits are processed usingvarious operations, including descrambling, deinterleaving and rateunmatching with LLR soft-combining using a circular buffer prior to LDPCdecoding. In at least one embodiment, descramble 5024 may involveprocesses that reverse one or more processes of scramble 5008. In atleast one embodiment, rate unmatch 5026 may involve processes thatreverse one or more processes of rate match 5006. In at least oneembodiment, descramble 5024 may receive output fromdemodulation/demapping 5022, and descramble received bits. In at leastone embodiment, rate unmatch 5026 may receive descrambled bits, andutilize LLR soft-combining utilizing a circular buffer prior to LDPCdecode 5028.

In at least one embodiment, decoding of LDPC codes in practicalapplications is done based on iterative belief propagation algorithms.In at least one embodiment, an LDPC code can be represented in a form ofa bipartite graph with parity check matrix H of size M×N being abiadjacency matrix defining connections between graph nodes. In at leastone embodiment, M rows of matrix H corresponds to parity check nodes,whereas N columns corresponds to variable nodes, i.e., received codewordbits. In at least one embodiment, a principle of belief propagationalgorithms is based on iterative message exchange, in which A Posterioriprobabilities between a variable and check nodes are updated, until avalid codeword is obtained. In at least one embodiment, LDPC decode 5028may output a transport block comprising data.

In at least one embodiment, CRC check 5030 may determine errors andperform one or more actions based on parity bits attached to a receivedtransport block. In at least one embodiment, CRC check 5030 may analyzeand process parity bits attached to a received transport block, orotherwise any information associated with a CRC. In at least oneembodiment, CRC check 5030 may transmit a processed transport block to aMAC layer for further processing.

It should be noted that, in various embodiments, transmitting andreceiving data, which may be a transport block or other variationthereof, may include various processes not depicted in FIG. 50 . In atleast one embodiment, processes depicted in FIG. 50 are not intended tobe exhaustive and further processes such as additional modulation,mapping, multiplexing, precoding, constellation mapping/demapping, MIMOdetection, detection, decoding and variations thereof may be utilized intransmitting and receiving data as part of a network. In at least oneembodiment, at least one component shown or described with respect toFIG. 50 is used to implement techniques and/or functions described inconnection with FIGS. 1-15B.

FIG. 51 illustrates an architecture of a system 5100 of a network inaccordance with some embodiments. In at least one embodiment, system5100 is shown to include a UE 5102, a 5G access node or RAN node (shownas (R)AN node 5108), a User Plane Function (shown as UPF 5104), a DataNetwork (DN 5106), which may be, for example, operator services,Internet access or 3rd party services, and a 5G Core Network (5GC)(shown as CN 5110).

In at least one embodiment, CN 5110 includes an Authentication ServerFunction (AUSF 5114); a Core Access and Mobility Management Function(AMF 5112); a Session Management Function (SMF 5118); a Network ExposureFunction (NEF 5116); a Policy Control Function (PCF 5122); a NetworkFunction (NF) Repository Function (NRF 5120); a Unified Data Management(UDM 5124); and an Application Function (AF 5126). In at least oneembodiment, CN 5110 may also include other elements that are not shown,such as a Structured Data Storage network function (SDSF), anUnstructured Data Storage network function (UDSF), and variationsthereof.

In at least one embodiment, UPF 5104 may act as an anchor point forintra-RAT and inter-RAT mobility, an external PDU session point ofinterconnect to DN 5106, and a branching point to support multi-homedPDU session. In at least one embodiment, UPF 5104 may also performpacket routing and forwarding, packet inspection, enforce user planepart of policy rules, lawfully intercept packets (UP collection);traffic usage reporting, perform QoS handling for user plane (e.g.packet filtering, gating, UL/DL rate enforcement), perform UplinkTraffic verification (e.g., SDF to QoS flow mapping), transport levelpacket marking in uplink and downlink, and downlink packet buffering anddownlink data notification triggering. In at least one embodiment, UPF5104 may include an uplink classifier to support routing traffic flowsto a data network. In at least one embodiment, DN 5106 may representvarious network operator services, Internet access, or third partyservices.

In at least one embodiment, AUSF 5114 may store data for authenticationof UE 5102 and handle authentication related functionality. In at leastone embodiment, AUSF 5114 may facilitate a common authenticationframework for various access types.

In at least one embodiment, AMF 5112 may be responsible for registrationmanagement (e.g., for registering UE 5102, etc.), connection management,reachability management, mobility management, and lawful interception ofAMF-related events, and access authentication and authorization. In atleast one embodiment, AMF 5112 may provide transport for SM messages forSMF 5118, and act as a transparent proxy for routing SM messages. In atleast one embodiment, AMF 5112 may also provide transport for shortmessage service (SMS) messages between UE 5102 and an SMS function(SMSF) (not shown by FIG. 51 ). In at least one embodiment, AMF 5112 mayact as Security Anchor Function (SEA), which may include interactionwith AUSF 5114 and UE 5102 and receipt of an intermediate key that wasestablished as a result of UE 5102 authentication process. In at leastone embodiment, where USIM based authentication is used, AMF 5112 mayretrieve security material from AUSF 5114. In at least one embodiment,AMF 5112 may also include a Security Context Management (SCM) function,which receives a key from SEA that it uses to derive access-networkspecific keys. In at least one embodiment, furthermore, AMF 5112 may bea termination point of RAN CP interface (N2 reference point), atermination point of NAS (NI) signaling, and perform NAS ciphering andintegrity protection.

In at least one embodiment, AMF 5112 may also support NAS signaling witha UE 5102 over an N3 interworking-function (IWF) interface. In at leastone embodiment, N3IWF may be used to provide access to untrustedentities. In at least one embodiment, N3IWF may be a termination pointfor N2 and N3 interfaces for control plane and user plane, respectively,and as such, may handle N2 signaling from SMF and AMF for PDU sessionsand QoS, encapsulate/de-encapsulate packets for IPSec and N3 tunneling,mark N3 user-plane packets in uplink, and enforce QoS corresponding toN3 packet marking taking into account QoS requirements associated tosuch marking received over N2. In at least one embodiment, N3IWF mayalso relay uplink and downlink control-plane NAS (NI) signaling betweenUE 5102 and AMF 5112, and relay uplink and downlink user-plane packetsbetween UE 5102 and UPF 5104. In at least one embodiment, N3IWF alsoprovides mechanisms for IPsec tunnel establishment with UE 5102.

In at least one embodiment, SMF 5118 may be responsible for sessionmanagement (e.g., session establishment, modify and release, includingtunnel maintain between UPF and AN node); UE IP address allocation &management (including optional Authorization); Selection and control ofUP function; Configures traffic steering at UPF to route traffic toproper destination; termination of interfaces towards Policy controlfunctions; control part of policy enforcement and QoS; lawful intercept(for SM events and interface to LI System); termination of SM parts ofNAS messages; downlink Data Notification; initiator of AN specific SMinformation, sent via AMF over N2 to AN; determine SSC mode of asession. In at least one embodiment, SMF 5118 may include followingroaming functionality: handle local enforcement to apply QoS SLAB(VPLMN); charging data collection and charging interface (VPLMN); lawfulintercept (in VPLMN for SM events and interface to LI System); supportfor interaction with external DN for transport of signaling for PDUsession authorization/authentication by external DN.

In at least one embodiment, NEF 5116 may provide means for securelyexposing services and capabilities provided by 3GPP network functionsfor third party, internal exposure/re-exposure, Application Functions(e.g., AF 5126), edge computing or fog computing systems, etc. In atleast one embodiment, NEF 5116 may authenticate, authorize, and/orthrottle AFs. In at least one embodiment, NEF 5116 may also translateinformation exchanged with AF 5126 and information exchanged withinternal network functions. In at least one embodiment, NEF 5116 maytranslate between an AF-Service-Identifier and an internal 5GCinformation. In at least one embodiment, NEF 5116 may also receiveinformation from other network functions (NFs) based on exposedcapabilities of other network functions. In at least one embodiment,this information may be stored at NEF 5116 as structured data, or at adata storage NF using a standardized interface. In at least oneembodiment, stored information can then be re-exposed by NEF 5116 toother NFs and AFs, and/or used for other purposes such as analytics.

In at least one embodiment, NRF 5120 may support service discoveryfunctions, receive NF Discovery Requests from NF instances, and provideinformation of discovered NF instances to NF instances. In at least oneembodiment, NRF 5120 also maintains information of available NFinstances and their supported services.

In at least one embodiment, PCF 5122 may provide policy rules to controlplane function(s) to enforce them, and may also support unified policyframework to govern network behavior. In at least one embodiment, PCF5122 may also implement a front end (FE) to access subscriptioninformation relevant for policy decisions in a UDR of UDM 5124.

In at least one embodiment, UDM 5124 may handle subscription-relatedinformation to support a network entities' handling of communicationsessions, and may store subscription data of UE 5102. In at least oneembodiment, UDM 5124 may include two parts, an application FE and a UserData Repository (UDR). In at least one embodiment, UDM may include a UDMFE, which is in charge of processing of credentials, locationmanagement, subscription management and so on. In at least oneembodiment, several different front ends may serve a same user indifferent transactions. In at least one embodiment, UDM-FE accessessubscription information stored in an UDR and performs authenticationcredential processing; user identification handling; accessauthorization; registration/mobility management; and subscriptionmanagement. In at least one embodiment, UDR may interact with PCF 5122.In at least one embodiment, UDM 5124 may also support SMS management,wherein an SMS-FE implements a similar application logic as discussedpreviously.

In at least one embodiment, AF 5126 may provide application influence ontraffic routing, access to a Network Capability Exposure (NCE), andinteract with a policy framework for policy control. In at least oneembodiment, NCE may be a mechanism that allows a 5GC and AF 5126 toprovide information to each other via NEF 5116, which may be used foredge computing implementations. In at least one embodiment, networkoperator and third party services may be hosted close to UE 5102 accesspoint of attachment to achieve an efficient service delivery through areduced end-to-end latency and load on a transport network. In at leastone embodiment, for edge computing implementations, 5GC may select a UPF5104 close to UE 5102 and execute traffic steering from UPF 5104 to DN5106 via N6 interface. In at least one embodiment, this may be based onUE subscription data, UE location, and information provided by AF 5126.In at least one embodiment, AF 5126 may influence UPF (re)selection andtraffic routing. In at least one embodiment, based on operatordeployment, when AF 5126 is considered to be a trusted entity, a networkoperator may permit AF 5126 to interact directly with relevant NFs.

In at least one embodiment, CN 5110 may include an SMSF, which may beresponsible for SMS subscription checking and verification, and relayingSM messages to/from UE 5102 to/from other entities, such as anSMS-GMSC/IWMSC/SMS-router. In at least one embodiment, SMS may alsointeract with AMF 5112 and UDM 5124 for notification procedure that UE5102 is available for SMS transfer (e.g., set a UE not reachable flag,and notifying UDM 5124 when UE 5102 is available for SMS).

In at least one embodiment, system 5100 may include followingservice-based interfaces: Namf: Service-based interface exhibited byAMF; Nsmf: Service-based interface exhibited by SMF; Nnef: Service-basedinterface exhibited by NEF; Npcf: Service-based interface exhibited byPCF; Nudm: Service-based interface exhibited by UDM; Naf: Service-basedinterface exhibited by AF; Nnrf: Service-based interface exhibited byNRF; and Nausf: Service-based interface exhibited by AUSF.

In at least one embodiment, system 5100 may include following referencepoints: N1: Reference point between UE and AMF; N2: Reference pointbetween (R)AN and AMF; N3: Reference point between (R)AN and UPF; N4:Reference point between SMF and UPF; and N6: Reference point between UPFand a Data Network. In at least one embodiment, there may be many morereference points and/or service-based interfaces between a NF servicesin NFs, however, these interfaces and reference points have been omittedfor clarity. In at least one embodiment, an NS reference point may bebetween a PCF and AF; an N7 reference point may be between PCF and SMF;an N11 reference point between AMF and SMF; etc. In at least oneembodiment, CN 5110 may include an Nx interface, which is an inter-CNinterface between MME and AMF 5112 in order to enable interworkingbetween CN 5110 and CN 7251.

In at least one embodiment, system 5100 may include multiple RAN nodes(such as (R)AN node 5108) wherein an Xn interface is defined between twoor more (R)AN node 5108 (e.g., gNBs) that connecting to 5GC 410, betweena (R)AN node 5108 (e.g., gNB) connecting to CN 5110 and an eNB (e.g., amacro RAN node), and/or between two eNBs connecting to CN 5110.

In at least one embodiment, Xn interface may include an Xn user plane(Xn-U) interface and an Xn control plane (Xn-C) interface. In at leastone embodiment, Xn-U may provide non-guar-anteed delivery of user planePDUs and support/provide data forwarding and flow control functionality.In at least one embodiment, Xn-C may provide management and errorhandling functionality, functionality to manage a Xn-C interface;mobility support for UE 5102 in a connected mode (e.g., CM-CONNECTED)including functionality to manage UE mobility for connected mode betweenone or more (R)AN node 5108. In at least one embodiment, mobilitysupport may include context transfer from an old (source) serving (R)ANnode 5108 to new (target) serving (R)AN node 5108; and control of userplane tunnels between old (source) serving (R)AN node 5108 to new(target) serving (R)AN node 5108.

In at least one embodiment, a protocol stack of a Xn-U may include atransport network layer built on Internet Protocol (IP) transport layer,and a GTP-U layer on top of a UDP and/or IP layer(s) to carry user planePDUs. In at least one embodiment, Xn-C protocol stack may include anapplication layer signaling protocol (referred to as Xn ApplicationProtocol (Xn-AP)) and a transport network layer that is built on an SCTPlayer. In at least one embodiment, SCTP layer may be on top of an IPlayer. In at least one embodiment, SCTP layer provides a guaranteeddelivery of application layer messages. In at least one embodiment, in atransport IP layer point-to-point transmission is used to deliversignaling PDUs. In at least one embodiment, Xn-U protocol stack and/or aXn-C protocol stack may be same or similar to a user plane and/orcontrol plane protocol stack(s) shown and described herein. In at leastone embodiment, at least one component shown or described with respectto FIG. 51 is used to implement techniques and/or functions described inconnection with FIGS. 1-15B.

FIG. 52 is an illustration of a control plane protocol stack inaccordance with some embodiments. In at least one embodiment, a controlplane 5200 is shown as a communications protocol stack between UE 4702(or alternatively, UE 4704), RAN 4716, and MME(s) 4728.

In at least one embodiment, PHY layer 5202 may transmit or receiveinformation used by MAC layer 5204 over one or more air interfaces. Inat least one embodiment, PHY layer 5202 may further perform linkadaptation or adaptive modulation and coding (AMC), power control, cellsearch (e.g., for initial synchronization and handover purposes), andother measurements used by higher layers, such as an RRC layer 5210. Inat least one embodiment, PHY layer 5202 may still further perform errordetection on transport channels, forward error correction (FEC)coding/de-coding of transport channels, modulation/demodulation ofphysical channels, interleaving, rate matching, mapping onto physicalchannels, and Multiple Input Multiple Output (MIMO) antenna processing.

In at least one embodiment, MAC layer 5204 may perform mapping betweenlogical channels and transport channels, multiplexing of MAC servicedata units (SDUs) from one or more logical channels onto transportblocks (TB) to be delivered to PHY via transport channels,de-multiplexing MAC SDUs to one or more logical channels from transportblocks (TB) delivered from PHY via transport channels, multiplexing MACSDUs onto TBs, scheduling information reporting, error correctionthrough hybrid automatic repeat request (HARD), and logical channelprioritization.

In at least one embodiment, RLC layer 5206 may operate in a plurality ofmodes of operation, including: Transparent Mode (TM), UnacknowledgedMode (UM), and Acknowledged Mode (AM). In at least one embodiment, RLClayer 5206 may execute transfer of upper layer protocol data units(PDUs), error correction through automatic repeat request (ARQ) for AMdata transfers, and concatenation, segmentation and reassembly of RLCSDUs for UM and AM data transfers. In at least one embodiment, RLC layer5206 may also execute re-segmentation of RLC data PDUs for AM datatransfers, reorder RLC data PDUs for UM and AM data transfers, detectduplicate data for UM and AM data transfers, discard RLC SDUs for UM andAM data transfers, detect protocol errors for AM data transfers, andperform RLC re-establishment.

In at least one embodiment, PDCP layer 5208 may execute headercompression and decompression of IP data, maintain PDCP Sequence Numbers(SNs), perform in-sequence delivery of upper layer PDUs atre-establishment of lower layers, eliminate duplicates of lower layerSDUs at re-establishment of lower layers for radio bearers mapped on RLCAM, cipher and decipher control plane data, perform integrity protectionand integrity verification of control plane data, control timer-baseddiscard of data, and perform security operations (e.g., ciphering,deciphering, integrity protection, integrity verification, etc.).

In at least one embodiment, main services and functions of a RRC layer5210 may include broadcast of system information (e.g., included inMaster Information Blocks (MIBs) or System Information Blocks (SIBs)related to a non-access stratum (NAS)), broadcast of system informationrelated to an access stratum (AS), paging, establishment, maintenanceand release of an RRC connection between an UE and E-UTRAN (e.g., RRCconnection paging, RRC connection establishment, RRC connectionmodification, and RRC connection release), establishment, configuration,maintenance and release of point-to-point radio bearers, securityfunctions including key management, inter radio access technology (RAT)mobility, and measurement configuration for UE measurement reporting. Inat least one embodiment, said MIBs and SIBs may comprise one or moreinformation elements (IEs), which may each comprise individual datafields or data structures.

In at least one embodiment, UE 4702 and RAN 4716 may utilize a Uuinterface (e.g., an LTE-Uu interface) to exchange control plane data viaa protocol stack comprising PHY layer 5202, MAC layer 5204, RLC layer5206, PDCP layer 5208, and RRC layer 5210.

In at least one embodiment, non-access stratum (NAS) protocols (NASprotocols 5212) form a highest stratum of a control plane between UE4702 and MME(s) 4728. In at least one embodiment, NAS protocols 5212support mobility of UE 4702 and session management procedures toestablish and maintain IP connectivity between UE 4702 and P-GW 4734.

In at least one embodiment, Si Application Protocol (S1-AP) layer (Si-APlayer 5222) may support functions of a Si interface and compriseElementary Procedures (EPs). In at least one embodiment, an EP is a unitof interaction between RAN 4716 and CN 4728. In at least one embodiment,S1-AP layer services may comprise two groups: UE-associated services andnon UE-associated services. In at least one embodiment, these servicesperform functions including, but not limited to: E-UTRAN Radio AccessBearer (E-RAB) management, UE capability indication, mobility, NASsignaling transport, RAN Information Management (RIM), and configurationtransfer.

In at least one embodiment, Stream Control Transmission Protocol (SCTP)layer (alternatively referred to as a stream control transmissionprotocol/internet protocol (SCTP/IP) layer) (SCTP layer 5220) may ensurereliable delivery of signaling messages between RAN 4716 and MME(s) 4728based, in part, on an IP protocol, supported by an IP layer 5218. In atleast one embodiment, L2 layer 5216 and an L1 layer 5214 may refer tocommunication links (e.g., wired or wireless) used by a RAN node and MMEto exchange information.

In at least one embodiment, RAN 4716 and MME(s) 4728 may utilize anS1-MIME interface to exchange control plane data via a protocol stackcomprising a L1 layer 5214, L2 layer 5216, IP layer 5218, SCTP layer5220, and Si-AP layer 5222. In at least one embodiment, at least onecomponent shown or described with respect to FIG. 52 is used toimplement techniques and/or functions described in connection with FIGS.1-15B.

FIG. 53 is an illustration of a user plane protocol stack in accordancewith at least one embodiment. In at least one embodiment, a user plane5300 is shown as a communications protocol stack between a UE 4702, RAN4716, S-GW 4730, and P-GW 4734. In at least one embodiment, user plane5300 may utilize a same protocol layers as control plane 5200. In atleast one embodiment, for example, UE 4702 and RAN 4716 may utilize a Uuinterface (e.g., an LTE-Uu interface) to exchange user plane data via aprotocol stack comprising PHY layer 5202, MAC layer 5204, RLC layer5206, PDCP layer 5208.

In at least one embodiment, General Packet Radio Service (GPRS)Tunneling Protocol for a user plane (GTP-U) layer (GTP-U layer 5304) maybe used for carrying user data within a GPRS core network and between aradio access network and a core network. In at least one embodiment,user data transported can be packets in any of IPv4, IPv6, or PPPformats, for example. In at least one embodiment, UDP and IP security(UDP/IP) layer (UDP/IP layer 5302) may provide checksums for dataintegrity, port numbers for addressing different functions at a sourceand destination, and encryption and authentication on selected dataflows. In at least one embodiment, RAN 4716 and S-GW 4730 may utilize anS1-U interface to exchange user plane data via a protocol stackcomprising L1 layer 5214, L2 layer 5216, UDP/IP layer 5302, and GTP-Ulayer 5304. In at least one embodiment, S-GW 4730 and P-GW 4734 mayutilize an S5/S8a interface to exchange user plane data via a protocolstack comprising L1 layer 5214, L2 layer 5216, UDP/IP layer 5302, andGTP-U layer 5304. In at least one embodiment, as discussed above withrespect to FIG. 52 , NAS protocols support a mobility of UE 4702 andsession management procedures to establish and maintain IP connectivitybetween UE 4702 and P-GW 4734. In at least one embodiment, at least onecomponent shown or described with respect to FIG. 53 is used toimplement techniques and/or functions described in connection with FIGS.1-15B.

FIG. 54 illustrates components 5400 of a core network in accordance withat least one embodiment. In at least one embodiment, components of CN4738 may be implemented in one physical node or separate physical nodesincluding components to read and execute instructions from amachine-readable or computer-readable medium (e.g., a non-transitorymachine-readable storage medium). In at least one embodiment, NetworkFunctions Virtualization (NFV) is utilized to virtualize any or all ofabove described network node functions via executable instructionsstored in one or more computer readable storage mediums (described infurther detail below). In at least one embodiment, a logicalinstantiation of CN 4738 may be referred to as a network slice 5402(e.g., network slice 5402 is shown to include HSS 4732, MME(s) 4728, andS-GW 4730). In at least one embodiment, a logical instantiation of aportion of CN 4738 may be referred to as a network sub-slice 5404 (e.g.,network sub-slice 5404 is shown to include P-GW 4734 and PCRF 4736).

In at least one embodiment, NFV architectures and infrastructures may beused to virtualize one or more network functions, alternativelyperformed by proprietary hardware, onto physical resources comprising acombination of industry-standard server hardware, storage hardware, orswitches. In at least one embodiment, NFV systems can be used to executevirtual or reconfigurable implementations of one or more EPCcomponents/functions. In at least one embodiment, at least one componentshown or described with respect to FIG. 54 is used to implementtechniques and/or functions described in connection with FIGS. 1-15B.

FIG. 55 is a block diagram illustrating components, according to atleast one embodiment, of a system 5500 to support network functionvirtualization (NFV). In at least one embodiment, system 5500 isillustrated as including a virtualized infrastructure manager (shown asVIM 5502), a network function virtualization infrastructure (shown asNFVI 5504), a VNF manager (shown as VNFM 5506), virtualized networkfunctions (shown as VNF 5508), an element manager (shown as EM 5510), anNFV Orchestrator (shown as NFVO 5512), and a network manager (shown asNM 5514).

In at least one embodiment, VIM 5502 manages resources of NFVI 5504. Inat least one embodiment, NFVI 5504 can include physical or virtualresources and applications (including hypervisors) used to executesystem 5500. In at least one embodiment, VIM 5502 may manage a lifecycle of virtual resources with NFVI 5504 (e.g., creation, maintenance,and tear down of virtual machines (VMs) associated with one or morephysical resources), track VM instances, track performance, fault andsecurity of VM instances and associated physical resources, and exposeVM instances and associated physical resources to other managementsystems.

In at least one embodiment, VNFM 5506 may manage VNF 5508. In at leastone embodiment, VNF 5508 may be used to execute EPCcomponents/functions. In at least one embodiment, VNFM 5506 may manage alife cycle of VNF 5508 and track performance, fault and security ofvirtual aspects of VNF 5508. In at least one embodiment, EM 5510 maytrack performance, fault and security of functional aspects of VNF 5508.In at least one embodiment, tracking data from VNFM 5506 and EM 5510 maycomprise, for example, performance measurement (PM) data used by VIM5502 or NFVI 5504. In at least one embodiment, both VNFM 5506 and EM5510 can scale up/down a quantity of VNFs of system 5500.

In at least one embodiment, NFVO 5512 may coordinate, authorize, releaseand engage resources of NFVI 5504 in order to provide a requestedservice (e.g., to execute an EPC function, component, or slice). In atleast one embodiment, NM 5514 may provide a package of end-userfunctions with responsibility for a management of a network, which mayinclude network elements with VNFs, non-virtualized network functions,or both (management of the VNFs may occur via the EM 5510).

In at least one embodiment, one or more components of systems and/orprocessors disclosed above can communicate with one or more CPUs, ASICs,GPUs, FPGAs, or other hardware, circuitry, or integrated circuitcomponents that include, e.g., an upscaler or upsampler to upscale animage, a sampler to sample an image (e.g., as part of a DSP), a neuralnetwork circuit that is configured to perform an upscaler to upscale animage (e.g., from a low resolution image to a high resolution image), orother hardware to modify or generate an image, frame, or video to adjustits resolution, size, or pixels; one or more components of systemsand/or processors disclosed above can use components described in thisdisclosure to perform methods, operations, or instructions that generateor modify an image. In at least one embodiment, at least one componentshown or described with respect to FIG. 55 is used to implementtechniques and/or functions described in connection with FIGS. 1-15B.

At least one embodiment of the disclosure can be described in view ofthe following clauses:

-   -   1. A processor comprising:    -   one or more circuits to perform an application programming        interface (API) to deselect storage selected to be used to        transfer information between a plurality of fifth generation new        radio (5G-NR) computing resources.    -   2. The processor of clause 1, wherein performance of the API        causes one or more of the 5G-NR computing resources to decrement        a reference counter used to indicate when to release the        selected storage.    -   3. The processor of any of clauses 1-2, wherein the information        is to be transferred between one of the plurality of 5G-NR        computing resources associated with a first information        transmission type and another 5G-NR computing resource of the        plurality of 5G-NR computing resources associated with a second        information transmission type.    -   4. The processor of any of clauses 1-3, wherein the one or more        circuits are further to perform the API without information        about a transmission type associated with one or more of the        5G-NR computing resources.    -   5. The processor of any of clauses 1-4, wherein performing the        API further causes one or more of the plurality of 5G-NR        computing resources to perform one or more operations associated        with a plurality of information transmission types associated        with one or more of the plurality of 5G-NR computing resources.    -   6. The processor of any of clauses 1-5, wherein the API is        based, at least in part, on information identifying an        information transmission type associated with one or more of the        plurality of 5G-NR computing resources.    -   7. The processor of any of clauses 1-6, wherein performing the        API is further to cause one or more of the plurality of 5G-NR        computing resources to perform an operation related to a first        information transmission type based, at least in part, on a        corresponding operation related to a second information        transmission type.    -   8. The processor of any of clauses 1-7, wherein:    -   the plurality of 5G-NR computing resources are associated with a        5G-NR network protocol stack that includes a first layer, a        second layer, and a third layer;    -   a first 5G-NR computing resource of the plurality of 5G-NR        computing resources is associated with the first layer;    -   a second 5G-NR computing resource of the plurality of 5G-NR        computing resources is associated with the second layer;    -   the API is associated with the third layer; and    -   the third layer is located between the first and second layers.    -   9. The processor of any of clauses 1-8, wherein:    -   the API is further to transfer information between a first layer        and a second layer corresponding to a 5G-NR network protocol,        wherein one or more of the plurality of 5G-NR computing        resources associated with the second layer requests an operation        associated with a first information transmission type; and    -   performance of the API causes one or more of the plurality of        5G-NR computing resources associated with the first layer to        perform an operation associated with a second transmission type.    -   10. A system, comprising memory to store instructions that, as a        result of execution by one or more processors, cause the system        to:    -   one or more circuits to perform an application programming        interface (API) to deselect storage selected to be used to        transfer information between a plurality of fifth generation new        radio (5G-NR) computing resources.    -   11. The system of clause 10, wherein performance of the API is        based, at least in part, on a transport protocol associated with        one of the plurality of 5G-NR computing resources.    -   12. The system of any of clauses 10-11, wherein:    -   the information is to be transferred between a first layer and a        second layer of a 5G-NR network protocol stack; and    -   the first layer and second layer are each associated with a        different transport protocol.    -   13. The system of any of clauses 10-12, wherein an application        associated with one of the plurality of 5G-NR computing        resources calls the API and does not have information regarding        any transport protocol supported by one or more of the plurality        of 5G-NR computing resources    -   14. The system of any of clauses 10-13, wherein the API is        embedded within another API    -   15. The system of any of clauses 10-14, wherein the information        is to be transferred using an application that causes calls from        one layer associated with one transport protocol to perform        operations in a second layer associated with a second transport        protocol.    -   16. The system of any of clauses 10-15, further comprising:    -   a network orchestrator configured to identify one or more        transport profiles supported by one of the plurality of 5G-NR        computing resources, and the network orchestrator is to deploy a        second of the plurality of 5G-NR computing resources with the        one 5G-NR computing resources configured with a transport        profile supported by the second 5G-NR computing resource.    -   17. The system of any of clauses 10-16, wherein one or more of        the plurality of 5G-NR resources is a virtual device.    -   18. A machine-readable medium having stored thereon one or more        instructions, which if performed by one or more processors,        cause one or more processors to at least:    -   one or more circuits to perform an application programming        interface (API) to deselect storage selected to be used to        transfer information between a plurality of fifth generation new        radio (5G-NR) computing resources.    -   19. The machine-readable medium of clause 18 wherein performance        of the API is based, at least in part, on a transport        configuration associated with one of the plurality of 5G-NR        computing resources.    -   20. The machine-readable medium any of clauses 18-19, wherein:    -   the information is to be transferred between a first layer and a        second layer of a 5G-NR network protocol stack using a third        layer between the first and second layers that is based, at        least in part, on multiple transport protocols.    -   21. The machine-readable medium of any of clauses 18-20, wherein        the one or more circuits are further to perform the API without        information associated with a transmission type associated with        one or more of the 5G-NR computing resources.    -   22. The machine-readable medium of any of clauses 18-21, wherein        the one or more processors are one or more graphics processing        units (GPUs).    -   23. The machine-readable medium of any of clauses 18-22,        wherein:    -   one of the plurality of 5G-NR computing resources is to call the        API; and    -   performance of the API causes, at least in part, the one 5G-NR        computing resource to transfer information to one or more other        of the plurality of 5G-NR computing resources that support        different transport protocols without modification to the one        5G-NR computing resource.    -   24. The machine-readable medium of any of clauses 18-23,        wherein:    -   the storage selected is an allocated buffer; and    -   performance of the API causes one or more of the plurality of        5G-NR computing resources to decrement a reference counter        associated with the allocated buffer; and    -   if the decremented reference counter holds a value of zero, the        allocated buffer is deselected.    -   25. The machine-readable medium of any of clauses 18-24, wherein        one of the plurality of 5G-NR computing resources has been        configured with a transport profile supported by a second of the        plurality of 5G-NR computing resources.    -   26. A method comprising:    -   perform an application programming interface (API) to deselect        storage selected to be used to transfer information between a        plurality of fifth generation new radio (5G-NR) computing        resources.    -   27. The method of clause 26, wherein performance of the API is        based, at least in part, on a transport profile associated with        one of the plurality of 5G-NR computing resources.    -   28. The method of any of clauses 26-27, further comprising        identifying one or more transport profiles supported by one or        more of the plurality of 5G-NR computing resources.    -   29. The method of any of clauses 26-28, further comprising:    -   configuring one 5G-NR computing resource of the plurality of        5G-NR computing resources with transport profiles supported by        the one 5G-NR computing resource; and    -   deploying the configured one 5G-NR computing resource with a        second 5G-NR computing resource.    -   30. The method of any of clauses 26-29, wherein the API is to be        called by one 5G-NR computing resource of the plurality of 5G-NR        computing resources that was deployed with a second 5G-NR        computing resource of the plurality of 5G-NR computing        resources, wherein the second 5G-NR computing resource was        configured with one or more transport profiles.    -   31. The method of any of clauses 26-30, further comprising        transferring the information using an application that maps the        API to an operation related to a transport protocol, wherein the        application is implemented, at least in part, on a hardware        accelerator.    -   32. The method of any of clauses 26-31, wherein performance of        the API causes one or more of the plurality of 5G-NR computing        resources to perform a buffer-related operation from a set of        buffer-related operations related to a plurality of transport        profiles.    -   33. The method of any of clauses 26-32, wherein:    -   the information is to be transferred between two layers of a        5G-NR network protocol stack, wherein each layer is associated        with a different transport protocol; and    -   the API is located in a third layer.    -   34. The method of any of clauses 26-33, wherein:    -   performance of the API causes one or more 5G-NR computing        resources to decrement a reference counter;    -   the reference counter is associated with the storage selected;        and    -   the storage selected is further to be used as part of a zero        copy buffer method.    -   35. The method of any of clauses 26-34, wherein the information        includes different messages each associated with a different        information transmission type; and    -   the information is to be transferred between two of the        plurality of 5G-NR computing resources using one transport.

Other variations are within spirit of present disclosure. Thus, whiledisclosed techniques are susceptible to various modifications andalternative constructions, certain illustrated embodiments thereof areshown in drawings and have been described above in detail. It should beunderstood, however, that there is no intention to limit disclosure tospecific form or forms disclosed, but on contrary, intention is to coverall modifications, alternative constructions, and equivalents fallingwithin spirit and scope of disclosure, as defined in appended claims.

Use of terms “a” and “an” and “the” and similar referents in context ofdescribing disclosed embodiments (especially in context of followingclaims) are to be construed to cover both singular and plural, unlessotherwise indicated herein or clearly contradicted by context, and notas a definition of a term. Terms “comprising,” “having,” “including,”and “containing” are to be construed as open-ended terms (meaning“including, but not limited to,”) unless otherwise noted. term“connected,” when unmodified and referring to physical connections, isto be construed as partly or wholly contained within, attached to, orjoined together, even if there is something intervening. Recitation ofranges of values herein are merely intended to serve as a shorthandmethod of referring individually to each separate value falling withinrange, unless otherwise indicated herein and each separate value isincorporated into specification as if it were individually recitedherein. In at least one embodiment, use of term “set” (e.g., “a set ofitems”) or “subset” unless otherwise noted or contradicted by context,is to be construed as a nonempty collection comprising one or moremembers. Further, unless otherwise noted or contradicted by context,term “subset” of a corresponding set does not necessarily denote aproper subset of corresponding set, but subset and corresponding set maybe equal.

Conjunctive language, such as phrases of form “at least one of A, B, andC,” or “at least one of A, B and C,” unless specifically statedotherwise or otherwise clearly contradicted by context, is otherwiseunderstood with context as used in general to present that an item,term, etc., may be either A or B or C, or any nonempty subset of set ofA and B and C. For instance, in illustrative example of a set havingthree members, conjunctive phrases “at least one of A, B, and C” and “atleast one of A, B and C” refer to any of following sets: {A}, {B}, {C},{A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctive language isnot generally intended to imply that certain embodiments require atleast one of A, at least one of B and at least one of C each to bepresent. In addition, unless otherwise noted or contradicted by context,term “plurality” indicates a state of being plural (e.g., “a pluralityof items” indicates multiple items). In at least one embodiment, numberof items in a plurality is at least two, but can be more when soindicated either explicitly or by context. Further, unless statedotherwise or otherwise clear from context, phrase “based on” means“based at least in part on” and not “based solely on.”

Operations of processes described herein can be performed in anysuitable order unless otherwise indicated herein or otherwise clearlycontradicted by context. In at least one embodiment, a process such asthose processes described herein (or variations and/or combinationsthereof) is performed under control of one or more computer systemsconfigured with executable instructions and is implemented as code(e.g., executable instructions, one or more computer programs or one ormore applications) executing collectively on one or more processors, byhardware or combinations thereof. In at least one embodiment, code isstored on a computer-readable storage medium, for example, in form of acomputer program comprising a plurality of instructions executable byone or more processors. In at least one embodiment, a computer-readablestorage medium is a non-transitory computer-readable storage medium thatexcludes transitory signals (e.g., a propagating transient electric orelectromagnetic transmission) but includes non-transitory data storagecircuitry (e.g., buffers, cache, and queues) within transceivers oftransitory signals. In at least one embodiment, code (e.g., executablecode or source code) is stored on a set of one or more non-transitorycomputer-readable storage media having stored thereon executableinstructions (or other memory to store executable instructions) that,when executed (i.e., as a result of being executed) by one or moreprocessors of a computer system, cause computer system to performoperations described herein. A set of non-transitory computer-readablestorage media, in at least one embodiment, comprises multiplenon-transitory computer-readable storage media and one or more ofindividual non-transitory storage media of multiple non-transitorycomputer-readable storage media lack all of code while multiplenon-transitory computer-readable storage media collectively store all ofcode. In at least one embodiment, executable instructions are executedsuch that different instructions are executed by differentprocessors—for example, a non-transitory computer-readable storagemedium store instructions and a main central processing unit (“CPU”)executes some of instructions while a graphics processing unit (“GPU”)executes other instructions. In at least one embodiment, differentcomponents of a computer system have separate processors and differentprocessors execute different subsets of instructions.

Accordingly, in at least one embodiment, computer systems are configuredto implement one or more services that singly or collectively performoperations of processes described herein and such computer systems areconfigured with applicable hardware and/or software that enableperformance of operations. Further, a computer system that implements atleast one embodiment of present disclosure is a single device and, inanother embodiment, is a distributed computer system comprising multipledevices that operate differently such that distributed computer systemperforms operations described herein and such that a single device doesnot perform all operations.

Use of any and all examples, or exemplary language (e.g., “such as”)provided herein, is intended merely to better illuminate embodiments ofdisclosure and does not pose a limitation on scope of disclosure unlessotherwise claimed. No language in specification should be construed asindicating any non-claimed element as essential to practice ofdisclosure.

All references, including publications, patent applications, andpatents, cited herein are hereby incorporated by reference to sameextent as if each reference were individually and specifically indicatedto be incorporated by reference and were set forth in its entiretyherein.

In description and claims, terms “coupled” and “connected,” along withtheir derivatives, may be used. It should be understood that these termsmay be not intended as synonyms for each other. Rather, in particularexamples, “connected” or “coupled” may be used to indicate that two ormore elements are in direct or indirect physical or electrical contactwith each other. “Coupled” may also mean that two or more elements arenot in direct contact with each other, but yet still co-operate orinteract with each other.

Unless specifically stated otherwise, it may be appreciated thatthroughout specification terms such as “processing,” “computing,”“calculating,” “determining,” or like, refer to action and/or processesof a computer or computing system, or similar electronic computingdevice, that manipulate and/or transform data represented as physical,such as electronic, quantities within computing system's registersand/or memories into other data similarly represented as physicalquantities within computing system's memories, registers or other suchinformation storage, transmission or display devices.

In a similar manner, term “processor” may refer to any device or portionof a device that processes electronic data from registers and/or memoryand transform that electronic data into other electronic data that maybe stored in registers and/or memory. As non-limiting examples,“processor” may be a CPU or a GPU. A “computing platform” may compriseone or more processors. As used herein, “software” processes mayinclude, for example, software and/or hardware entities that performwork over time, such as tasks, threads, and intelligent agents. Also,each process may refer to multiple processes, for carrying outinstructions in sequence or in parallel, continuously or intermittently.Terms “system” and “method” are used herein interchangeably insofar assystem may embody one or more methods and methods may be considered asystem.

In at least one embodiment, an arithmetic logic unit is a set ofcombinational logic circuitry that takes one or more inputs to produce aresult. In at least one embodiment, an arithmetic logic unit is used bya processor to implement mathematical operation such as addition,subtraction, or multiplication. In at least one embodiment, anarithmetic logic unit is used to implement logical operations such aslogical AND/OR or XOR. In at least one embodiment, an arithmetic logicunit is stateless, and made from physical switching components such assemiconductor transistors arranged to form logical gates. In at leastone embodiment, an arithmetic logic unit may operate internally as astateful logic circuit with an associated clock. In at least oneembodiment, an arithmetic logic unit may be constructed as anasynchronous logic circuit with an internal state not maintained in anassociated register set. In at least one embodiment, an arithmetic logicunit is used by a processor to combine operands stored in one or moreregisters of the processor and produce an output that can be stored bythe processor in another register or a memory location.

In at least one embodiment, as a result of processing an instructionretrieved by the processor, the processor presents one or more inputs oroperands to an arithmetic logic unit, causing the arithmetic logic unitto produce a result based at least in part on an instruction codeprovided to inputs of the arithmetic logic unit. In at least oneembodiment, the instruction codes provided by the processor to the ALUare based at least in part on the instruction executed by the processor.In at least one embodiment combinational logic in the ALU processes theinputs and produces an output which is placed on a bus within theprocessor. In at least one embodiment, the processor selects adestination register, memory location, output device, or output storagelocation on the output bus so that clocking the processor causes theresults produced by the ALU to be sent to the desired location.

In the scope of this application, the term arithmetic logic unit, orALU, is used to refer to any computational logic circuit that processesoperands to produce a result. For example, in the present document, theterm ALU can refer to a floating point unit, a DSP, a tensor core, ashader core, a coprocessor, or a CPU.

In present document, references may be made to obtaining, acquiring,receiving, or inputting analog or digital data into a subsystem,computer system, or computer-implemented machine. A process ofobtaining, acquiring, receiving, or inputting analog and digital datacan be accomplished in a variety of ways such as by receiving data as aparameter of a function call or a call to an application programminginterface. In some implementations, process of obtaining, acquiring,receiving, or inputting analog or digital data can be accomplished bytransferring data via a serial or parallel interface. In anotherimplementation, process of obtaining, acquiring, receiving, or inputtinganalog or digital data can be accomplished by transferring data via acomputer network from providing entity to acquiring entity. Referencesmay also be made to providing, outputting, transmitting, sending, orpresenting analog or digital data. In various examples, process ofproviding, outputting, transmitting, sending, or presenting analog ordigital data can be accomplished by transferring data as an input oroutput parameter of a function call, a parameter of an applicationprogramming interface or interprocess communication mechanism.

Although discussion above sets forth example implementations ofdescribed techniques, other architectures may be used to implementdescribed functionality, and are intended to be within scope of thisdisclosure. Furthermore, although specific distributions ofresponsibilities are defined above for purposes of discussion, variousfunctions and responsibilities might be distributed and divided indifferent ways, depending on circumstances.

Furthermore, although subject matter has been described in languagespecific to structural features and/or methodological acts, it is to beunderstood that subject matter claimed in appended claims is notnecessarily limited to specific features or acts described. Rather,specific features and acts are disclosed as exemplary forms ofimplementing the claims.

What is claimed is:
 1. A processor comprising: one or more circuits toperform an application programming interface (API) to deselect storageselected to be used to transfer information between a plurality of fifthgeneration new radio (5G-NR) computing resources.
 2. The processor ofclaim 1, wherein performance of the API causes one or more of the 5G-NRcomputing resources to decrement a reference counter used to indicatewhen to release the selected storage.
 3. The processor of claim 1,wherein the information is to be transferred between one of theplurality of 5G-NR computing resources associated with a firstinformation transmission type and another 5G-NR computing resource ofthe plurality of 5G-NR computing resources associated with a secondinformation transmission type.
 4. The processor of claim 1, wherein theone or more circuits are further to perform the API without informationabout a transmission type associated with one or more of the 5G-NRcomputing resources.
 5. The processor of claim 1, wherein performing theAPI further causes one or more of the plurality of 5G-NR computingresources to perform one or more operations associated with a pluralityof information transmission types associated with one or more of theplurality of 5G-NR computing resources.
 6. The processor of claim 1,wherein the API is based, at least in part, on information identifyingan information transmission type associated with one or more of theplurality of 5G-NR computing resources.
 7. The processor of claim 1,wherein performing the API is further to cause one or more of theplurality of 5G-NR computing resources to perform an operation relatedto a first information transmission type based, at least in part, on acorresponding operation related to a second information transmissiontype.
 8. The processor of claim 1, wherein: the plurality of 5G-NRcomputing resources are associated with a 5G-NR network protocol stackthat includes a first layer, a second layer, and a third layer; a first5G-NR computing resource of the plurality of 5G-NR computing resourcesis associated with the first layer; a second 5G-NR computing resource ofthe plurality of 5G-NR computing resources is associated with the secondlayer; the API is associated with the third layer; and the third layeris located between the first and second layers.
 9. The processor ofclaim 1, wherein: the API is further to transfer information between afirst layer and a second layer corresponding to a 5G-NR networkprotocol, wherein one or more of the plurality of 5G-NR computingresources associated with the second layer requests an operationassociated with a first information transmission type; and performanceof the API causes one or more of the plurality of 5G-NR computingresources associated with the first layer to perform an operationassociated with a second transmission type.
 10. A system, comprisingmemory to store instructions that, as a result of execution by one ormore processors, cause the system to: one or more circuits to perform anapplication programming interface (API) to deselect storage selected tobe used to transfer information between a plurality of fifth generationnew radio (5G-NR) computing resources.
 11. The system of claim 10,wherein performance of the API is based, at least in part, on atransport protocol associated with one of the plurality of 5G-NRcomputing resources.
 12. The system of claim 10, wherein: theinformation is to be transferred between a first layer and a secondlayer of a 5G-NR network protocol stack; and the first layer and secondlayer are each associated with a different transport protocol.
 13. Thesystem of claim 10, wherein an application associated with one of theplurality of 5G-NR computing resources calls the API and does not haveinformation regarding any transport protocol supported by one or more ofthe plurality of 5G-NR computing resources.
 14. The system of claim 10,wherein the API is embedded within another API.
 15. The system of claim10, wherein the information is to be transferred using an applicationthat causes calls from one layer associated with one transport protocolto perform operations in a second layer associated with a secondtransport protocol.
 16. The system of claim 10, further comprising: anetwork orchestrator configured to identify one or more transportprofiles supported by one of the plurality of 5G-NR computing resources,and the network orchestrator is to deploy a second of the plurality of5G-NR computing resources with the one 5G-NR computing resourcesconfigured with a transport profile supported by the second 5G-NRcomputing resource.
 17. The system of claim 10, wherein one or more ofthe plurality of 5G-NR resources is a virtual device.
 18. Amachine-readable medium having stored thereon one or more instructions,which if performed by one or more processors, cause one or moreprocessors to at least: one or more circuits to perform an applicationprogramming interface (API) to deselect storage selected to be used totransfer information between a plurality of fifth generation new radio(5G-NR) computing resources.
 19. The machine-readable medium of claim18, wherein performance of the API is based, at least in part, on atransport configuration associated with one of the plurality of 5G-NRcomputing resources.
 20. The machine-readable medium of claim 18,wherein: the information is to be transferred between a first layer anda second layer of a 5G-NR network protocol stack using a third layerbetween the first and second layers that is based, at least in part, onmultiple transport protocols.
 21. The machine-readable medium of claim18, wherein the one or more circuits are further to perform the APIwithout information associated with a transmission type associated withone or more of the 5G-NR computing resources.
 22. The machine-readablemedium of claim 18, wherein the one or more processors are one or moregraphics processing units (GPUs).
 23. The machine-readable medium ofclaim 18, wherein: one of the plurality of 5G-NR computing resources isto call the API; and performance of the API causes, at least in part,the one 5G-NR computing resource to transfer information to one or moreother of the plurality of 5G-NR computing resources that supportdifferent transport protocols without modification to the one 5G-NRcomputing resource.
 24. The machine-readable medium of claim 18,wherein: the storage selected is an allocated buffer; and performance ofthe API causes one or more of the plurality of 5G-NR computing resourcesto decrement a reference counter associated with the allocated buffer;and if the decremented reference counter holds a value of zero, theallocated buffer is deselected.
 25. The machine-readable medium of claim18, wherein one of the plurality of 5G-NR computing resources has beenconfigured with a transport profile supported by a second of theplurality of 5G-NR computing resources.
 26. A method comprising: performan application programming interface (API) to deselect storage selectedto be used to transfer information between a plurality of fifthgeneration new radio (5G-NR) computing resources.
 27. The method ofclaim 26, wherein performance of the API is based, at least in part, ona transport profile associated with one of the plurality of 5G-NRcomputing resources.
 28. The method of claim 26, further comprisingidentifying one or more transport profiles supported by one or more ofthe plurality of 5G-NR computing resources.
 29. The method of claim 26,further comprising: configuring one 5G-NR computing resource of theplurality of 5G-NR computing resources with transport profiles supportedby the one 5G-NR computing resource; and deploying the configured one5G-NR computing resource with a second 5G-NR computing resource.
 30. Themethod of claim 26, wherein the API is to be called by one 5G-NRcomputing resource of the plurality of 5G-NR computing resources thatwas deployed with a second 5G-NR computing resource of the plurality of5G-NR computing resources, wherein the second 5G-NR computing resourcewas configured with one or more transport profiles.
 31. The method ofclaim 26, further comprising transferring the information using anapplication that maps the API to an operation related to a transportprotocol, wherein the application is implemented, at least in part, on ahardware accelerator.
 32. The method of claim 26, wherein the API isembedded within another API.
 33. The method of claim 26, wherein: theinformation is to be transferred between two layers of a 5G-NR networkprotocol stack, wherein each layer is associated with a differenttransport protocol; and the API is located in a third layer.
 34. Themethod of claim 26, wherein: performance of the API causes one or more5G-NR computing resources to decrement a reference counter; thereference counter is associated with the storage selected; and thestorage selected is further to be used as part of a zero copy buffermethod.
 35. The method of claim 26, wherein the information includesdifferent messages each associated with a different informationtransmission type; and the information is to be transferred between twoof the plurality of 5G-NR computing resources using one transport.